Lines Matching refs:ports
256 struct usb_hub_descriptor *desc, int ports)
262 desc->bNbrPorts = ports;
272 /* Bits 6:5 - no TTs in root ports */
281 int ports;
289 ports = rhub->num_ports;
290 xhci_common_hub_descriptor(xhci, desc, ports);
292 temp = 1 + (ports / 8);
300 for (i = 0; i < ports; i++) {
301 portsc = readl(rhub->ports[i]->addr);
313 * ports on it. The USB 2.0 specification says that there are two
316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
320 * set of ports that actually exist.
327 for (i = 0; i < (ports + 1 + 7) / 8; i++)
336 int ports;
343 ports = rhub->num_ports;
344 xhci_common_hub_descriptor(xhci, desc, ports);
357 for (i = 0; i < ports; i++) {
358 portsc = readl(rhub->ports[i]->addr);
414 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
588 /* Don't allow the USB core to disable SuperSpeed ports. */
715 /* xhci only supports test mode for usb2 ports */
716 port = xhci->usb2_rhub.ports[wIndex];
745 /* Put all ports to the Disable state by clear PP */
747 /* Power off USB3 ports*/
749 xhci_set_port_power(xhci, xhci->usb3_rhub.ports[i], false, flags);
750 /* Power off USB2 ports*/
752 xhci_set_port_power(xhci, xhci->usb2_rhub.ports[i], false, flags);
901 * This Function verifies if all xhc USB3 ports have entered U0, if so,
919 "All USB3 ports have entered U0 already!");
1160 port = rhub->ports[wIndex];
1212 struct xhci_port **ports;
1217 ports = rhub->ports;
1258 port = ports[portnum1 - 1];
1303 port = ports[portnum1 - 1];
1491 * Turn on ports, even if there isn't per-port switching.
1553 port = ports[portnum1 - 1];
1650 struct xhci_port **ports;
1653 ports = rhub->ports;
1684 temp = readl(ports[i]->addr);
1694 (ports[i]->resume_timestamp && time_after_eq(
1695 jiffies, ports[i]->resume_timestamp))) {
1722 struct xhci_port **ports;
1727 ports = rhub->ports;
1744 * Prepare ports for suspend, but don't write anything before all ports
1753 t1 = readl(ports[port_index]->addr);
1777 /* suspend ports in U0, or bail out for new connect changes */
1818 /* write port settings, stopping and suspending ports if needed */
1834 writel(portsc_buf[port_index], ports[port_index]->addr);
1885 struct xhci_port **ports;
1888 ports = rhub->ports;
1906 /* bus specific resume for ports we suspended at bus_suspend */
1914 portsc = readl(ports[port_index]->addr);
1916 /* warm reset CAS limited ports stuck in polling/compliance */
1919 xhci_port_missing_cas_quirk(ports[port_index])) {
1942 /* disable wake for all ports, write new link state if needed */
1944 writel(portsc, ports[port_index]->addr);
1957 xhci_test_and_clear_bit(xhci, ports[port_index],
1959 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1965 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1972 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1995 return rhub->bus_state.resuming_ports; /* USB2 ports only */