Lines Matching defs:temp
258 u16 temp;
263 temp = 0;
266 temp |= HUB_CHAR_INDV_PORT_LPSM;
268 temp |= HUB_CHAR_NO_LPSM;
271 temp |= HUB_CHAR_INDV_PORT_OCPM;
274 desc->wHubCharacteristics = cpu_to_le16(temp);
282 u16 temp;
292 temp = 1 + (ports / 8);
293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
681 u32 temp;
684 temp = readl(port->addr);
687 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp);
689 temp = xhci_port_state_to_neutral(temp);
693 writel(temp | PORT_POWER, port->addr);
697 writel(temp & ~PORT_POWER, port->addr);
701 temp = usb_acpi_power_manageable(hcd->self.root_hub,
703 if (temp)
712 u32 temp;
717 temp = readl(port->addr + PORTPMSC);
718 temp |= test_mode << PORT_TEST_MODE_SHIFT;
719 writel(temp, port->addr + PORTPMSC);
790 u32 temp;
794 temp = xhci_port_state_to_neutral(portsc);
795 temp &= ~PORT_PLS_MASK;
796 temp |= PORT_LINK_STROBE | link_state;
797 writel(temp, port->addr);
801 portsc, temp);
807 u32 temp;
809 temp = readl(port->addr);
810 temp = xhci_port_state_to_neutral(temp);
813 temp |= PORT_WKCONN_E;
815 temp &= ~PORT_WKCONN_E;
818 temp |= PORT_WKDISC_E;
820 temp &= ~PORT_WKDISC_E;
823 temp |= PORT_WKOC_E;
825 temp &= ~PORT_WKOC_E;
827 writel(temp, port->addr);
834 u32 temp;
836 temp = readl(port->addr);
837 if (temp & port_bit) {
838 temp = xhci_port_state_to_neutral(temp);
839 temp |= port_bit;
840 writel(temp, port->addr);
1203 u32 temp, status;
1259 temp = readl(port->addr);
1260 if (temp == ~(u32)0) {
1265 trace_xhci_get_port_status(wIndex, temp);
1266 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1272 hcd->self.busnum, portnum1, temp, status);
1285 status = xhci_get_ext_port_status(temp, port_li);
1305 temp = readl(port->addr);
1306 if (temp == ~(u32)0) {
1311 temp = xhci_port_state_to_neutral(temp);
1315 temp = readl(port->addr);
1316 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1327 temp = readl(port->addr);
1328 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1329 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1352 temp = readl(port->addr);
1356 temp = readl(port->addr);
1361 temp = xhci_port_state_to_neutral(temp);
1366 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1369 writel(temp | PORT_PE, port->addr);
1370 temp = readl(port->addr);
1379 temp = readl(port->addr);
1403 if ((temp & PORT_CONNECT)) {
1412 temp = readl(port->addr);
1416 if (!(temp & PORT_PE)) {
1435 u32 pls = temp & PORT_PLS_MASK;
1460 temp = readl(port->addr);
1480 temp = readl(port->addr);
1481 if ((temp & PORT_PLS_MASK) == XDEV_U3)
1485 temp = readl(port->addr);
1499 temp = (temp | PORT_RESET);
1500 writel(temp, port->addr);
1502 temp = readl(port->addr);
1504 hcd->self.busnum, portnum1, temp);
1508 temp = readl(port->addr);
1510 hcd->self.busnum, portnum1, temp);
1513 temp |= PORT_WR;
1514 writel(temp, port->addr);
1515 temp = readl(port->addr);
1520 temp = readl(port->addr + PORTPMSC);
1521 temp &= ~PORT_U1_TIMEOUT_MASK;
1522 temp |= PORT_U1_TIMEOUT(timeout);
1523 writel(temp, port->addr + PORTPMSC);
1528 temp = readl(port->addr + PORTPMSC);
1529 temp &= ~PORT_U2_TIMEOUT_MASK;
1530 temp |= PORT_U2_TIMEOUT(timeout);
1531 writel(temp, port->addr + PORTPMSC);
1547 temp = readl(port->addr);
1556 temp = readl(port->addr);
1557 if (temp == ~(u32)0) {
1563 temp = xhci_port_state_to_neutral(temp);
1566 temp = readl(port->addr);
1568 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1569 if (temp & PORT_RESET)
1571 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1572 if ((temp & PORT_PE) == 0)
1606 port->addr, temp);
1642 u32 temp, status;
1684 temp = readl(ports[i]->addr);
1685 if (temp == ~(u32)0) {
1690 trace_xhci_hub_status_data(i, temp);
1692 if ((temp & mask) != 0 ||
1699 if ((temp & PORT_RC))
1701 if (temp & PORT_OC)
1883 u32 temp, portsc;
1902 temp = readl(&xhci->op_regs->command);
1903 temp &= ~CMD_EIE;
1904 writel(temp, &xhci->op_regs->command);
1981 temp = readl(&xhci->op_regs->command);
1982 temp |= CMD_EIE;
1983 writel(temp, &xhci->op_regs->command);
1984 temp = readl(&xhci->op_regs->command);