Lines Matching refs:UDCCR
105 tmp = udc_readl(udc, UDCCR);
192 tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR);
270 * - we rely on UDCCR register "active interface" and "active altsetting".
358 * udc_set_mask_UDCCR - set bits in UDCCR
360 * @mask: bits to set in UDCCR
362 * Sets bits in UDCCR, leaving DME and FST bits as they were.
366 u32 udccr = udc_readl(udc, UDCCR);
367 udc_writel(udc, UDCCR,
372 * udc_clear_mask_UDCCR - clears bits in UDCCR
374 * @mask: bit to clear in UDCCR
376 * Clears bits in UDCCR, leaving DME and FST bits as they were.
380 u32 udccr = udc_readl(udc, UDCCR);
381 udc_writel(udc, UDCCR,
388 * @mask: bits to set in UDCCR
528 * Find the physical pxa27x ep, and setup its UDCCR
543 udc_ep_writel(ep, UDCCR, new_udccr);
1459 if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0)
1712 if (udc_readl(udc, UDCCR) & UDCCR_EMCE)
2215 u32 udccr = udc_readl(udc, UDCCR);
2239 u32 udccr = udc_readl(udc, UDCCR);
2270 u32 udccr = udc_readl(udc, UDCCR);
2274 "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr);
2469 if (udc_readl(udc, UDCCR) & UDCCR_UDE)
2479 * Suspends udc : saves configuration registers (UDCCR*), then disables the udc
2504 * Resumes udc : restores configuration registers (UDCCR*), then enables the udc