Lines Matching refs:ep0state
563 dev->ep0state = EP0_IDLE;
883 switch (dev->ep0state) {
900 dev->ep0state = EP0_END_XFER;
915 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
1033 ep->dev->ep0state = EP0_STALL;
1385 dev->ep0state = EP0_IDLE;
1580 if (dev->ep0state == EP0_STALL
1615 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1621 switch (dev->ep0state) {
1697 dev->ep0state = EP0_IN_DATA_PHASE;
1699 dev->ep0state = EP0_OUT_DATA_PHASE;
1726 dev->ep0state = EP0_STALL;
1730 if (likely(dev->ep0state == EP0_IN_DATA_PHASE