Lines Matching refs:uframe
52 #define FOTG210_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
562 /* uframe masks */
708 temp = scnprintf(next, size, "uframe %04x\n",
2741 * - allowing for high bandwidth, how many nsec/uframe are used?
2742 * - split transactions need a second CSPLIT uframe; same question
3330 /* how many of the uframe's 125 usecs are allocated? */
3332 unsigned frame, unsigned uframe)
3344 if (hw->hw_info2 & cpu_to_hc32(fotg210, 1 << uframe))
3348 1 << (8 + uframe)))
3365 if (q->itd->hw_transaction[uframe])
3373 fotg210_err(fotg210, "uframe %d sched overrun: %d usecs\n",
3374 frame * 8 + uframe, usecs);
3401 * (different dev or endpoint) until the next uframe.
3474 * this just links in a qh; caller guarantees uframe masks are set right.
3668 unsigned uframe, unsigned period, unsigned usecs)
3675 if (uframe >= 8)
3681 /* we "know" 2 and 4 uframe intervals were rejected; so
3686 for (uframe = 0; uframe < 7; uframe++) {
3688 uframe);
3694 /* just check the specified uframe, at that period */
3697 claimed = periodic_usecs(fotg210, frame, uframe);
3708 unsigned uframe, const struct fotg210_qh *qh, __hc32 *c_maskp)
3713 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
3716 if (!check_period(fotg210, frame, uframe, qh->period, qh->usecs))
3731 mask = 0x03 << (uframe + qh->gap_uf);
3734 mask |= 1 << uframe;
3736 if (!check_period(fotg210, frame, uframe + qh->gap_uf + 1,
3739 if (!check_period(fotg210, frame, uframe + qh->gap_uf,
3754 unsigned uframe;
3765 uframe = ffs(hc32_to_cpup(fotg210, &hw->hw_info2) & QH_SMASK);
3766 status = check_intr_schedule(fotg210, frame, --uframe,
3769 uframe = 0;
3784 for (uframe = 0; uframe < 8; uframe++) {
3786 frame, uframe, qh,
3793 /* qh->period == 0 means every uframe */
3806 ? cpu_to_hc32(fotg210, 1 << uframe)
4031 /* figure out per-uframe itd fields that we'll need later
4035 struct fotg210_iso_packet *uframe = &iso_sched->packet[i];
4049 uframe->transaction = cpu_to_hc32(fotg210, trans);
4051 /* might need to cross a buffer page within a uframe */
4052 uframe->bufp = (buf & ~(u64)0x0fff);
4054 if (unlikely((uframe->bufp != (buf & ~(u64)0x0fff))))
4055 uframe->cross = 1;
4130 static inline int itd_slot_ok(struct fotg210_hcd *fotg210, u32 mod, u32 uframe,
4133 uframe %= period;
4136 if (periodic_usecs(fotg210, uframe >> 3, uframe & 0x7)
4141 uframe += period;
4142 } while (uframe < mod);
4227 /* find a uframe slot with enough bandwidth.
4298 unsigned index, u16 uframe)
4303 uframe &= 0x07;
4304 itd->index[uframe] = index;
4306 itd->hw_transaction[uframe] = uf->transaction;
4307 itd->hw_transaction[uframe] |= cpu_to_hc32(fotg210, pg << 12);
4352 unsigned next_uframe, uframe, frame;
4369 /* fill iTDs uframe by uframe */
4374 /* ASSERT: no itds for this endpoint in this uframe */
4384 uframe = next_uframe & 0x07;
4387 itd_patch(fotg210, itd, iso_sched, packet, uframe);
4429 unsigned uframe;
4435 /* for each uframe with a packet */
4436 for (uframe = 0; uframe < 8; uframe++) {
4437 if (likely(itd->index[uframe] == -1))
4439 urb_index = itd->index[uframe];
4442 t = hc32_to_cpup(fotg210, &itd->hw_transaction[uframe]);
4443 itd->hw_transaction[uframe] = 0;
4696 unsigned frame, uframe;
4730 for (uframe = 0; uframe < 7; ++uframe)
4733 uframe));
4746 "setting max periodic bandwidth to %u%% (== %u usec/uframe)\n",
4915 * by default set standard 80% (== 100 usec/uframe) max periodic