Lines Matching refs:trb
161 * dwc3_ep_inc_trb - increment a trb index.
206 if (req->trb)
210 req->trb = NULL;
482 struct dwc3_trb *trb)
484 u32 offset = (char *) trb - (char *) dep->trb_pool;
500 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
935 struct dwc3_trb *trb;
940 trb = &dep->trb_pool[0];
941 trb_dma = dwc3_trb_dma_offset(dep, trb);
1236 struct dwc3_trb *trb;
1253 trb = &dep->trb_pool[dep->trb_enqueue];
1255 if (!req->trb) {
1257 req->trb = trb;
1258 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1263 trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1264 trb->bpl = lower_32_bits(dma);
1265 trb->bph = upper_32_bits(dma);
1269 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1274 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1309 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1312 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1316 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1321 trb->ctrl = DWC3_TRBCTL_NORMAL;
1338 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1341 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1346 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1349 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1352 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1355 trb->ctrl |= DWC3_TRB_CTRL_LST;
1358 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1373 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1377 trace_dwc3_prepare_trb(dep, trb);
1505 * queued because of insufficient trb number. To handle this
2026 /* If req->trb is not set, then the request has not started */
2027 if (!req->trb)
2041 struct dwc3_trb *trb;
2043 trb = &dep->trb_pool[dep->trb_dequeue];
2044 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2167 struct dwc3_trb *trb;
2173 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2175 trb = &dwc->ep0_trb[dep->trb_enqueue];
2177 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
3360 struct dwc3_request *req, struct dwc3_trb *trb,
3367 trace_dwc3_complete_trb(dep, trb);
3380 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3381 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3388 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3391 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3401 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3402 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3403 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3407 count = trb->size & DWC3_TRB_SIZE_MASK;
3410 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3416 if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3417 DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3420 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3421 (trb->ctrl & DWC3_TRB_CTRL_LST))
3431 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3439 trb = &dep->trb_pool[dep->trb_dequeue];
3445 trb, event, status, true);
3457 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3459 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3500 struct dwc3_trb *trb;
3502 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3503 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
4586 dev_err(dwc->dev, "failed to allocate ep0 trb\n");