Lines Matching defs:exynos
3 * dwc3-exynos.c - Samsung Exynos DWC3 Specific Glue layer
42 struct dwc3_exynos *exynos;
48 exynos = devm_kzalloc(dev, sizeof(*exynos), GFP_KERNEL);
49 if (!exynos)
53 exynos->dev = dev;
54 exynos->num_clks = driver_data->num_clks;
55 exynos->clk_names = (const char **)driver_data->clk_names;
56 exynos->suspend_clk_idx = driver_data->suspend_clk_idx;
58 platform_set_drvdata(pdev, exynos);
60 for (i = 0; i < exynos->num_clks; i++) {
61 exynos->clks[i] = devm_clk_get(dev, exynos->clk_names[i]);
62 if (IS_ERR(exynos->clks[i])) {
64 exynos->clk_names[i]);
65 return PTR_ERR(exynos->clks[i]);
69 for (i = 0; i < exynos->num_clks; i++) {
70 ret = clk_prepare_enable(exynos->clks[i]);
73 clk_disable_unprepare(exynos->clks[i]);
78 if (exynos->suspend_clk_idx >= 0)
79 clk_prepare_enable(exynos->clks[exynos->suspend_clk_idx]);
81 exynos->vdd33 = devm_regulator_get(dev, "vdd33");
82 if (IS_ERR(exynos->vdd33)) {
83 ret = PTR_ERR(exynos->vdd33);
86 ret = regulator_enable(exynos->vdd33);
92 exynos->vdd10 = devm_regulator_get(dev, "vdd10");
93 if (IS_ERR(exynos->vdd10)) {
94 ret = PTR_ERR(exynos->vdd10);
97 ret = regulator_enable(exynos->vdd10);
118 regulator_disable(exynos->vdd10);
120 regulator_disable(exynos->vdd33);
122 for (i = exynos->num_clks - 1; i >= 0; i--)
123 clk_disable_unprepare(exynos->clks[i]);
125 if (exynos->suspend_clk_idx >= 0)
126 clk_disable_unprepare(exynos->clks[exynos->suspend_clk_idx]);
133 struct dwc3_exynos *exynos = platform_get_drvdata(pdev);
138 for (i = exynos->num_clks - 1; i >= 0; i--)
139 clk_disable_unprepare(exynos->clks[i]);
141 if (exynos->suspend_clk_idx >= 0)
142 clk_disable_unprepare(exynos->clks[exynos->suspend_clk_idx]);
144 regulator_disable(exynos->vdd33);
145 regulator_disable(exynos->vdd10);
193 struct dwc3_exynos *exynos = dev_get_drvdata(dev);
196 for (i = exynos->num_clks - 1; i >= 0; i--)
197 clk_disable_unprepare(exynos->clks[i]);
199 regulator_disable(exynos->vdd33);
200 regulator_disable(exynos->vdd10);
207 struct dwc3_exynos *exynos = dev_get_drvdata(dev);
210 ret = regulator_enable(exynos->vdd33);
215 ret = regulator_enable(exynos->vdd10);
221 for (i = 0; i < exynos->num_clks; i++) {
222 ret = clk_prepare_enable(exynos->clks[i]);
225 clk_disable_unprepare(exynos->clks[i]);
246 .name = "exynos-dwc3",