Lines Matching refs:hsotg
38 * @hsotg: The HCD state structure for the DWC OTG controller
42 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
52 num_channels = hsotg->params.host_channels;
53 if ((hsotg->periodic_channels + hsotg->non_periodic_channels <
54 num_channels) && (hsotg->periodic_channels < num_channels - 1)) {
57 dev_dbg(hsotg->dev,
60 hsotg->periodic_channels, hsotg->non_periodic_channels);
71 * @hsotg: The HCD state structure for the DWC OTG controller
79 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
101 if (hsotg->periodic_usecs > max_claimed_usecs) {
102 dev_err(hsotg->dev,
104 __func__, hsotg->periodic_usecs, qh->host_us);
334 * @hsotg: The HCD state structure for the DWC OTG controller.
340 * add logic here to get a map out of "hsotg" if !qh->do_split.
344 static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
462 struct dwc2_hsotg *hsotg;
476 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
482 * @hsotg: The HCD state structure for the DWC OTG controller.
485 static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
488 struct dwc2_qh_print_data print_data = { hsotg, qh };
498 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
500 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
506 dwc2_sch_dbg(hsotg,
522 dwc2_sch_dbg(hsotg,
527 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
528 pmap_print(hsotg->hs_periodic_bitmap,
535 static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
542 * @hsotg: The HCD state structure for the DWC OTG controller.
554 static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
558 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
590 * @hsotg: The HCD state structure for the DWC OTG controller.
593 static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
597 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
617 * @hsotg: The HCD state structure for the DWC OTG controller.
628 static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
634 us = pmap_schedule(hsotg->hs_periodic_bitmap,
650 * @hsotg: The HCD state structure for the DWC OTG controller.
654 static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
659 pmap_unschedule(hsotg->hs_periodic_bitmap,
675 * @hsotg: The HCD state structure for the DWC OTG controller.
678 static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
719 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
754 dwc2_ls_pmap_unschedule(hsotg, qh);
827 dwc2_sch_dbg(hsotg,
831 dwc2_ls_pmap_unschedule(hsotg, qh);
926 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
936 dwc2_hs_pmap_unschedule(hsotg, qh, i);
939 dwc2_ls_pmap_unschedule(hsotg, qh);
957 * @hsotg: The HCD state structure for the DWC OTG controller.
960 static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
971 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
980 * @hsotg: The HCD state structure for the DWC OTG controller.
983 static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
991 return dwc2_ls_pmap_schedule(hsotg, qh, 0);
1000 * @hsotg: The HCD state structure for the DWC OTG controller.
1003 static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1008 ret = dwc2_uframe_schedule_hs(hsotg, qh);
1010 ret = dwc2_uframe_schedule_ls(hsotg, qh);
1012 ret = dwc2_uframe_schedule_split(hsotg, qh);
1015 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
1017 dwc2_qh_schedule_print(hsotg, qh);
1025 * @hsotg: The HCD state structure for the DWC OTG controller.
1028 static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1033 dwc2_hs_pmap_unschedule(hsotg, qh, i);
1036 dwc2_ls_pmap_unschedule(hsotg, qh);
1038 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1052 * @hsotg: The HCD state structure for the DWC OTG controller
1056 static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1068 frame_number = dwc2_hcd_get_frame_number(hsotg);
1082 if (!hsotg->params.uframe_sched) {
1156 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1166 * @hsotg: The HCD state structure for the DWC OTG controller
1171 static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1175 if (hsotg->params.uframe_sched) {
1176 status = dwc2_uframe_schedule(hsotg, qh);
1178 status = dwc2_periodic_channel_available(hsotg);
1180 dev_info(hsotg->dev,
1186 status = dwc2_check_periodic_bandwidth(hsotg, qh);
1190 dev_dbg(hsotg->dev,
1196 if (!hsotg->params.uframe_sched)
1198 hsotg->periodic_channels++;
1201 hsotg->periodic_usecs += qh->host_us;
1203 dwc2_pick_first_frame(hsotg, qh);
1214 * @hsotg: The HCD state structure for the DWC OTG controller
1217 static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1219 assert_spin_locked(&hsotg->lock);
1230 hsotg->periodic_usecs -= qh->host_us;
1232 if (hsotg->params.uframe_sched) {
1233 dwc2_uframe_unschedule(hsotg, qh);
1236 hsotg->periodic_channels--;
1255 struct dwc2_hsotg *hsotg = qh->hsotg;
1267 while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
1283 dwc2_do_unreserve(hsotg, qh);
1285 spin_unlock_irqrestore(&hsotg->lock, flags);
1293 * @hsotg: The HCD state structure for the DWC OTG controller
1298 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1306 max_channel_xfer_size = hsotg->params.max_transfer_size;
1309 dev_err(hsotg->dev,
1322 * @hsotg: The HCD state structure for the DWC OTG controller
1328 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1332 status = dwc2_check_max_xfer_size(hsotg, qh);
1334 dev_dbg(hsotg->dev,
1352 status = dwc2_do_reserve(hsotg, qh);
1363 hsotg->frame_number))
1364 dwc2_pick_first_frame(hsotg, qh);
1369 if (hsotg->params.dma_desc_enable)
1371 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1375 &hsotg->periodic_sched_inactive);
1384 * @hsotg: The HCD state structure for the DWC OTG controller
1387 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1392 assert_spin_locked(&hsotg->lock);
1443 struct dwc2_hsotg *hsotg = qh->hsotg;
1446 spin_lock_irqsave(&hsotg->lock, flags);
1458 &hsotg->non_periodic_sched_inactive);
1460 tr_type = dwc2_hcd_select_transactions(hsotg);
1462 dwc2_hcd_queue_transactions(hsotg, tr_type);
1465 spin_unlock_irqrestore(&hsotg->lock, flags);
1472 * @hsotg: The HCD state structure for the DWC OTG controller
1478 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1481 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1486 u32 hprt = dwc2_readl(hsotg, HPRT0);
1496 qh->hsotg = hsotg;
1515 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1587 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
1589 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
1594 dwc2_sch_dbg(hsotg,
1597 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1600 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1601 qh, dwc2_get_ls_map(hsotg, qh));
1608 * @hsotg: The HCD state structure for the DWC OTG controller
1615 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1629 dwc2_qh_init(hsotg, qh, urb, mem_flags);
1631 if (hsotg->params.dma_desc_enable &&
1632 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1633 dwc2_hcd_qh_free(hsotg, qh);
1643 * @hsotg: HCD instance
1651 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1657 spin_lock_irqsave(&hsotg->lock, flags);
1658 dwc2_do_unreserve(hsotg, qh);
1659 spin_unlock_irqrestore(&hsotg->lock, flags);
1671 dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
1674 dwc2_hcd_qh_free_ddma(hsotg, qh);
1675 else if (hsotg->unaligned_cache && qh->dw_align_buf)
1676 kmem_cache_free(hsotg->unaligned_cache, qh->dw_align_buf);
1686 * @hsotg: The HCD state structure for the DWC OTG controller
1691 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1698 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1707 qh->start_active_frame = hsotg->frame_number;
1712 &hsotg->non_periodic_sched_waiting);
1718 &hsotg->non_periodic_sched_inactive);
1723 status = dwc2_schedule_periodic(hsotg, qh);
1726 if (!hsotg->periodic_qh_count) {
1727 intr_mask = dwc2_readl(hsotg, GINTMSK);
1729 dwc2_writel(hsotg, intr_mask, GINTMSK);
1731 hsotg->periodic_qh_count++;
1740 * @hsotg: The HCD state structure
1743 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1747 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1757 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1758 hsotg->non_periodic_qh_ptr =
1759 hsotg->non_periodic_qh_ptr->next;
1764 dwc2_deschedule_periodic(hsotg, qh);
1765 hsotg->periodic_qh_count--;
1766 if (!hsotg->periodic_qh_count &&
1767 !hsotg->params.dma_desc_enable) {
1768 intr_mask = dwc2_readl(hsotg, GINTMSK);
1770 dwc2_writel(hsotg, intr_mask, GINTMSK);
1787 * @hsotg: The HCD state structure
1793 static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1850 * @hsotg: The HCD state structure
1856 static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1947 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1955 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1958 dwc2_hcd_qh_unlink(hsotg, qh);
1961 dwc2_hcd_qh_add(hsotg, qh);
1971 frame_number = dwc2_hcd_get_frame_number(hsotg);
1974 missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
1976 missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
1978 dwc2_sch_vdbg(hsotg,
1986 dwc2_hcd_qh_unlink(hsotg, qh);
1994 * Note: we purposely use the frame_number from the "hsotg" structure
1997 if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
1999 &hsotg->periodic_sched_ready);
2002 &hsotg->periodic_sched_inactive);
2039 * @hsotg: The DWC HCD structure
2048 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2054 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2059 retval = dwc2_hcd_qh_add(hsotg, qh);