Lines Matching refs:hsotg
33 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
35 u16 curr_frame_number = hsotg->frame_number;
36 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
39 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
43 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
45 hsotg->frame_num_array[hsotg->frame_num_idx] =
47 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
48 hsotg->last_frame_num;
49 hsotg->frame_num_idx++;
51 } else if (!hsotg->dumped_frame_num_array) {
54 dev_info(hsotg->dev, "Frame Last Frame\n");
55 dev_info(hsotg->dev, "----- ----------\n");
57 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
58 hsotg->frame_num_array[i],
59 hsotg->last_frame_num_array[i]);
61 hsotg->dumped_frame_num_array = 1;
64 hsotg->last_frame_num = curr_frame_number;
67 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
71 struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
110 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
117 dwc2_writel(hsotg, GINTSTS_SOF, GINTSTS);
120 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
123 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
125 dwc2_track_missed_sofs(hsotg);
128 qh_entry = hsotg->periodic_sched_inactive.next;
129 while (qh_entry != &hsotg->periodic_sched_inactive) {
133 hsotg->frame_number)) {
134 dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
135 qh, hsotg->frame_number,
143 &hsotg->periodic_sched_ready);
146 tr_type = dwc2_hcd_select_transactions(hsotg);
148 dwc2_hcd_queue_transactions(hsotg, tr_type);
156 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
162 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
164 grxsts = dwc2_readl(hsotg, GRXSTSP);
166 chan = hsotg->hc_ptr_array[chnum];
168 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
178 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
179 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
180 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
182 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
189 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
202 dev_err(hsotg->dev,
214 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
216 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
217 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
226 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
229 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
230 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
233 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
236 struct dwc2_core_params *params = &hsotg->params;
244 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
247 hfir = dwc2_readl(hsotg, HFIR);
249 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
251 dwc2_writel(hsotg, hfir, HFIR);
256 hsotg->flags.b.port_reset_change = 1;
260 usbcfg = dwc2_readl(hsotg, GUSBCFG);
268 dwc2_writel(hsotg, usbcfg, GUSBCFG);
272 hcfg = dwc2_readl(hsotg, HCFG);
279 dev_vdbg(hsotg->dev,
285 dwc2_writel(hsotg, hcfg, HCFG);
290 dev_vdbg(hsotg->dev,
296 dwc2_writel(hsotg, hcfg, HCFG);
304 dwc2_writel(hsotg, usbcfg, GUSBCFG);
311 dwc2_writel(hsotg, *hprt0_modify, HPRT0);
312 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
316 hsotg->flags.b.port_reset_change = 1;
325 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
330 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
332 hprt0 = dwc2_readl(hsotg, HPRT0);
347 dwc2_writel(hsotg, hprt0_modify | HPRT0_CONNDET, HPRT0);
349 dev_vdbg(hsotg->dev,
352 dwc2_hcd_connect(hsotg);
365 dwc2_writel(hsotg, hprt0_modify | HPRT0_ENACHG, HPRT0);
366 dev_vdbg(hsotg->dev,
370 hsotg->new_connection = true;
371 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
373 hsotg->flags.b.port_enable_change = 1;
374 if (hsotg->params.dma_desc_fs_enable) {
377 hsotg->params.dma_desc_enable = false;
378 hsotg->new_connection = false;
379 hcfg = dwc2_readl(hsotg, HCFG);
381 dwc2_writel(hsotg, hcfg, HCFG);
388 dwc2_writel(hsotg, hprt0_modify | HPRT0_OVRCURRCHG,
390 dev_vdbg(hsotg->dev,
393 hsotg->flags.b.port_over_current_change = 1;
406 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
414 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
451 * @hsotg: Programming view of the DWC_otg controller
460 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
468 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
473 dev_dbg(hsotg->dev, "%s(): trimming xfer length\n", __func__);
477 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
491 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
492 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
494 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
495 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
497 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
498 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
499 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
510 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
514 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
545 * @hsotg: Programming view of the DWC_otg controller
555 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
570 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
589 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
595 hsotg->params.host_dma) {
602 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
612 dwc2_host_complete(hsotg, qtd, 0);
628 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
635 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
636 hsotg, qh, free_qtd);
639 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
652 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
658 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
664 * @hsotg: The HCD state structure
674 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
684 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
698 dev_vdbg(hsotg->dev,
701 dwc2_host_complete(hsotg, qtd, -EPROTO);
712 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
714 dwc2_host_complete(hsotg, qtd, -EIO);
721 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
731 dwc2_hc_cleanup(hsotg, chan);
732 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
734 if (hsotg->params.uframe_sched) {
735 hsotg->available_host_channels++;
740 hsotg->non_periodic_channels--;
753 haintmsk = dwc2_readl(hsotg, HAINTMSK);
755 dwc2_writel(hsotg, haintmsk, HAINTMSK);
758 tr_type = dwc2_hcd_select_transactions(hsotg);
760 dwc2_hcd_queue_transactions(hsotg, tr_type);
773 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
778 dev_vdbg(hsotg->dev, "%s()\n", __func__);
780 if (hsotg->params.host_dma) {
782 dev_vdbg(hsotg->dev, "DMA enabled\n");
783 dwc2_release_channel(hsotg, chan, qtd, halt_status);
788 dwc2_hc_halt(hsotg, chan, halt_status);
793 dev_vdbg(hsotg->dev, "Halt on queue\n");
796 dev_vdbg(hsotg->dev, "control/bulk\n");
802 gintmsk = dwc2_readl(hsotg, GINTMSK);
804 dwc2_writel(hsotg, gintmsk, GINTMSK);
806 dev_vdbg(hsotg->dev, "isoc/intr\n");
814 &hsotg->periodic_sched_assigned);
821 gintmsk = dwc2_readl(hsotg, GINTMSK);
823 dwc2_writel(hsotg, gintmsk, GINTMSK);
833 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
838 dev_vdbg(hsotg->dev, "%s()\n", __func__);
848 dev_vdbg(hsotg->dev, "got NYET\n");
868 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
874 dwc2_release_channel(hsotg, chan, qtd, halt_status);
883 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
888 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
894 dwc2_release_channel(hsotg, chan, qtd, halt_status);
897 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
900 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
913 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
923 dev_vdbg(hsotg->dev, "non-aligned buffer\n");
924 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
932 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
943 dwc2_host_complete(hsotg, qtd, 0);
944 dwc2_release_channel(hsotg, chan, qtd,
947 dwc2_release_channel(hsotg, chan, qtd,
958 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
968 dev_vdbg(hsotg->dev,
977 if (hsotg->params.dma_desc_enable) {
978 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
988 hsotg->params.host_dma) {
990 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1007 dev_vdbg(hsotg->dev,
1012 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1016 dev_vdbg(hsotg->dev,
1019 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1025 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1028 dwc2_host_complete(hsotg, qtd, urb->status);
1033 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1037 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1038 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1041 dwc2_host_complete(hsotg, qtd, urb->status);
1047 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1048 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1052 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1053 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1061 dwc2_host_complete(hsotg, qtd, urb->status);
1067 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1068 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1073 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1075 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1078 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1084 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1091 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1098 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1101 if (hsotg->params.dma_desc_enable) {
1102 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1113 dwc2_host_complete(hsotg, qtd, -EPIPE);
1117 dwc2_host_complete(hsotg, qtd, -EPIPE);
1129 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1132 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1141 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1147 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1152 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1158 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1159 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1161 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1163 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1165 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1166 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1168 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1170 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1178 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1183 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1188 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1193 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1223 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1230 if (hsotg->params.host_dma && chan->ep_is_in) {
1249 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1251 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1262 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1266 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1270 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1275 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1283 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1290 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1301 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1344 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1352 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1362 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1367 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1376 hsotg->params.host_dma) {
1382 dwc2_host_complete(hsotg, qtd, 0);
1383 dwc2_release_channel(hsotg, chan, qtd,
1386 dwc2_release_channel(hsotg, chan, qtd,
1397 if (!hsotg->params.uframe_sched) {
1398 int frnum = dwc2_hcd_get_frame_number(hsotg);
1454 dwc2_halt_channel(hsotg, chan, qtd,
1461 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1468 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1470 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1476 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1479 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1486 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1490 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1493 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1495 if (hsotg->params.dma_desc_enable) {
1496 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1502 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1503 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1507 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1509 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1513 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1520 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1531 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1537 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1539 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1540 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1541 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1542 hc_dma = dwc2_readl(hsotg, HCDMA(chnum));
1544 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1545 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1546 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1547 dev_err(hsotg->dev, " Device address: %d\n",
1549 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1571 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1588 dev_err(hsotg->dev, " Speed: %s\n", speed);
1590 dev_err(hsotg->dev, " Max packet size: %d (mult %d)\n",
1593 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1594 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1596 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1598 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1601 if (hsotg->params.dma_desc_enable) {
1602 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1607 dwc2_host_complete(hsotg, qtd, -EIO);
1614 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1617 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1624 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1628 dev_dbg(hsotg->dev,
1631 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1633 if (hsotg->params.dma_desc_enable) {
1634 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1644 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1646 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1655 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1661 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1667 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1669 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1675 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1682 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1689 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1692 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1699 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1702 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1704 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1708 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1715 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1719 dev_dbg(hsotg->dev,
1725 dev_err(hsotg->dev,
1729 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1730 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1740 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1755 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1756 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1757 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1758 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1759 dev_dbg(hsotg->dev,
1762 dev_dbg(hsotg->dev,
1765 dev_dbg(hsotg->dev,
1769 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1771 dev_warn(hsotg->dev,
1782 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1784 dev_warn(hsotg->dev,
1788 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1800 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1808 dev_vdbg(hsotg->dev,
1816 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1826 !hsotg->params.dma_desc_enable)) {
1827 if (hsotg->params.dma_desc_enable)
1828 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1837 dwc2_release_channel(hsotg, chan, qtd,
1842 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1853 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1854 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1856 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1858 !hsotg->params.dma_desc_enable) {
1862 dev_vdbg(hsotg->dev,
1866 dev_vdbg(hsotg->dev,
1876 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1878 hsotg->params.dma_desc_enable) {
1879 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1881 hsotg->params.dma_desc_enable) {
1882 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1884 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1886 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1895 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1905 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1915 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1925 dev_dbg(hsotg->dev,
1928 dwc2_halt_channel(hsotg, chan, qtd,
1931 dev_err(hsotg->dev,
1934 dev_err(hsotg->dev,
1937 dwc2_readl(hsotg, GINTSTS));
1942 dev_info(hsotg->dev,
1948 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1962 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1963 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1978 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1983 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1986 if (hsotg->params.host_dma) {
1987 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1989 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1991 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
2014 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2020 chan = hsotg->hc_ptr_array[chnum];
2022 hcintraw = dwc2_readl(hsotg, HCINT(chnum));
2023 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
2025 dwc2_writel(hsotg, hcint, HCINT(chnum));
2028 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2033 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2035 dev_vdbg(hsotg->dev,
2045 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2062 if (hsotg->params.dma_desc_enable)
2063 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2066 dwc2_release_channel(hsotg, chan, NULL,
2076 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2078 dev_dbg(hsotg->dev,
2082 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2090 if (!hsotg->params.host_dma) {
2096 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2106 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2111 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2116 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2121 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2126 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2131 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2136 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2141 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2146 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2151 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2166 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2172 haint = dwc2_readl(hsotg, HAINT);
2174 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2176 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2185 list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2190 dwc2_hc_n_intr(hsotg, hc_num);
2195 for (i = 0; i < hsotg->params.host_channels; i++) {
2197 dwc2_hc_n_intr(hsotg, i);
2202 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2207 if (!dwc2_is_controller_alive(hsotg)) {
2208 dev_warn(hsotg->dev, "Controller is dead\n");
2214 spin_lock(&hsotg->lock);
2217 if (dwc2_is_host_mode(hsotg)) {
2218 gintsts = dwc2_read_core_intr(hsotg);
2220 spin_unlock(&hsotg->lock);
2236 dev_vdbg(hsotg->dev,
2241 dwc2_sof_intr(hsotg);
2243 dwc2_rx_fifo_level_intr(hsotg);
2245 dwc2_np_tx_fifo_empty_intr(hsotg);
2247 dwc2_port_intr(hsotg);
2249 dwc2_hc_intr(hsotg);
2251 dwc2_perio_tx_fifo_empty_intr(hsotg);
2254 dev_vdbg(hsotg->dev,
2256 dev_vdbg(hsotg->dev,
2258 dwc2_readl(hsotg, GINTSTS),
2259 dwc2_readl(hsotg, GINTMSK));
2263 spin_unlock(&hsotg->lock);