Lines Matching refs:hsotg
58 static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
65 desc_cache = hsotg->desc_hsisoc_cache;
67 desc_cache = hsotg->desc_gen_cache;
76 qh->desc_list_dma = dma_map_single(hsotg->dev, qh->desc_list,
82 dma_unmap_single(hsotg->dev, qh->desc_list_dma,
93 static void dwc2_desc_list_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
99 desc_cache = hsotg->desc_hsisoc_cache;
101 desc_cache = hsotg->desc_gen_cache;
104 dma_unmap_single(hsotg->dev, qh->desc_list_dma,
114 static int dwc2_frame_list_alloc(struct dwc2_hsotg *hsotg, gfp_t mem_flags)
116 if (hsotg->frame_list)
119 hsotg->frame_list_sz = 4 * FRLISTEN_64_SIZE;
120 hsotg->frame_list = kzalloc(hsotg->frame_list_sz, GFP_ATOMIC | GFP_DMA);
121 if (!hsotg->frame_list)
124 hsotg->frame_list_dma = dma_map_single(hsotg->dev, hsotg->frame_list,
125 hsotg->frame_list_sz,
131 static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg)
135 spin_lock_irqsave(&hsotg->lock, flags);
137 if (!hsotg->frame_list) {
138 spin_unlock_irqrestore(&hsotg->lock, flags);
142 dma_unmap_single(hsotg->dev, hsotg->frame_list_dma,
143 hsotg->frame_list_sz, DMA_FROM_DEVICE);
145 kfree(hsotg->frame_list);
146 hsotg->frame_list = NULL;
148 spin_unlock_irqrestore(&hsotg->lock, flags);
151 static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
156 spin_lock_irqsave(&hsotg->lock, flags);
158 hcfg = dwc2_readl(hsotg, HCFG);
161 spin_unlock_irqrestore(&hsotg->lock, flags);
165 dwc2_writel(hsotg, hsotg->frame_list_dma, HFLBADDR);
169 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
170 dwc2_writel(hsotg, hcfg, HCFG);
172 spin_unlock_irqrestore(&hsotg->lock, flags);
175 static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
180 spin_lock_irqsave(&hsotg->lock, flags);
182 hcfg = dwc2_readl(hsotg, HCFG);
185 spin_unlock_irqrestore(&hsotg->lock, flags);
190 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
191 dwc2_writel(hsotg, hcfg, HCFG);
193 spin_unlock_irqrestore(&hsotg->lock, flags);
200 static void dwc2_update_frame_list(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
206 if (!hsotg) {
207 pr_err("hsotg = %p\n", hsotg);
212 dev_err(hsotg->dev, "qh->channel = %p\n", qh->channel);
216 if (!hsotg->frame_list) {
217 dev_err(hsotg->dev, "hsotg->frame_list = %p\n",
218 hsotg->frame_list);
232 hsotg->frame_list[j] |= 1 << chan->hc_num;
234 hsotg->frame_list[j] &= ~(1 << chan->hc_num);
242 dma_sync_single_for_device(hsotg->dev,
243 hsotg->frame_list_dma,
244 hsotg->frame_list_sz,
264 static void dwc2_release_channel_ddma(struct dwc2_hsotg *hsotg,
270 if (hsotg->params.uframe_sched)
271 hsotg->available_host_channels++;
273 hsotg->non_periodic_channels--;
275 dwc2_update_frame_list(hsotg, qh, 0);
276 hsotg->available_host_channels++;
286 dwc2_hc_cleanup(hsotg, chan);
287 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
303 * @hsotg: The HCD state structure for the DWC OTG controller
312 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
318 dev_err(hsotg->dev,
324 retval = dwc2_desc_list_alloc(hsotg, qh, mem_flags);
330 if (!hsotg->frame_list) {
331 retval = dwc2_frame_list_alloc(hsotg, mem_flags);
335 dwc2_per_sched_enable(hsotg, HCFG_FRLISTEN_64);
343 dwc2_desc_list_free(hsotg, qh);
352 * @hsotg: The HCD state structure for the DWC OTG controller
358 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
362 dwc2_desc_list_free(hsotg, qh);
371 spin_lock_irqsave(&hsotg->lock, flags);
373 dwc2_release_channel_ddma(hsotg, qh);
374 spin_unlock_irqrestore(&hsotg->lock, flags);
378 (hsotg->params.uframe_sched ||
379 !hsotg->periodic_channels) && hsotg->frame_list) {
380 dwc2_per_sched_disable(hsotg);
381 dwc2_frame_list_free(hsotg);
398 static u16 dwc2_calc_starting_frame(struct dwc2_hsotg *hsotg,
403 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
432 if (dwc2_micro_frame_num(hsotg->frame_number) >= 5) {
434 frame = dwc2_frame_num_inc(hsotg->frame_number,
438 frame = dwc2_frame_num_inc(hsotg->frame_number,
450 frame = dwc2_frame_num_inc(hsotg->frame_number, 2);
460 static u16 dwc2_recalc_initial_desc_idx(struct dwc2_hsotg *hsotg,
484 frame = dwc2_calc_starting_frame(hsotg, qh, &skip_frames);
495 qh->next_active_frame = dwc2_calc_starting_frame(hsotg, qh,
511 static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
543 dma_sync_single_for_device(hsotg->dev,
550 static void dwc2_init_isoc_dma_desc(struct dwc2_hsotg *hsotg,
561 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
562 cur_idx = dwc2_frame_list_idx(hsotg->frame_number);
574 dev_vdbg(hsotg->dev,
601 dwc2_fill_host_isoc_dma_desc(hsotg, qtd, qh,
617 dma_sync_single_for_device(hsotg->dev,
651 dma_sync_single_for_device(hsotg->dev,
659 static void dwc2_fill_host_dma_desc(struct dwc2_hsotg *hsotg,
693 dma_sync_single_for_device(hsotg->dev,
711 static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
718 dev_vdbg(hsotg->dev, "%s(): qh=%p dma=%08lx len=%d\n", __func__, qh,
729 dev_vdbg(hsotg->dev, "qtd=%p\n", qtd);
737 dev_vdbg(hsotg->dev, "buf=%08lx len=%d\n",
745 dev_vdbg(hsotg->dev,
749 dma_sync_single_for_device(hsotg->dev,
756 dwc2_fill_host_dma_desc(hsotg, chan, qtd, qh, n_desc);
757 dev_vdbg(hsotg->dev,
767 dev_vdbg(hsotg->dev, "n_desc=%d\n", n_desc);
778 dev_vdbg(hsotg->dev, "set IOC/EOL/A bits in desc %d (%p)\n",
780 dma_sync_single_for_device(hsotg->dev,
787 dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n",
789 dma_sync_single_for_device(hsotg->dev,
801 * @hsotg: The HCD state structure for the DWC OTG controller
817 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
826 dwc2_init_non_isoc_dma_desc(hsotg, qh);
827 dwc2_hc_start_transfer_ddma(hsotg, chan);
830 dwc2_init_non_isoc_dma_desc(hsotg, qh);
831 dwc2_update_frame_list(hsotg, qh, 1);
832 dwc2_hc_start_transfer_ddma(hsotg, chan);
836 skip_frames = dwc2_recalc_initial_desc_idx(hsotg, qh);
837 dwc2_init_isoc_dma_desc(hsotg, qh, skip_frames);
840 dwc2_update_frame_list(hsotg, qh, 1);
850 dwc2_hc_start_transfer_ddma(hsotg, chan);
862 static int dwc2_cmpl_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
875 dma_sync_single_for_cpu(hsotg->dev, qh->desc_list_dma + (idx *
908 dwc2_host_complete(hsotg, qtd, 0);
909 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
931 static void dwc2_complete_isoc_xfer_ddma(struct dwc2_hsotg *hsotg,
973 dwc2_host_complete(hsotg, qtd, err);
976 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
992 dev_vdbg(hsotg->dev,
1002 rc = dwc2_cmpl_host_isoc_dma_desc(hsotg, chan, qtd, qh,
1020 cur_idx = dwc2_frame_list_idx(hsotg->frame_number);
1037 static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg,
1051 dev_vdbg(hsotg->dev, "remain=%d dwc2_urb=%p\n", remain, urb);
1054 dev_err(hsotg->dev, "EIO\n");
1062 dev_vdbg(hsotg->dev, "Stall\n");
1066 dev_err(hsotg->dev, "Babble\n");
1070 dev_err(hsotg->dev, "XactErr\n");
1074 dev_err(hsotg->dev,
1083 dev_vdbg(hsotg->dev,
1108 dev_vdbg(hsotg->dev, "length=%d actual=%d\n", urb->length,
1119 static int dwc2_process_non_isoc_desc(struct dwc2_hsotg *hsotg,
1132 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1137 dma_sync_single_for_cpu(hsotg->dev,
1145 dev_vdbg(hsotg->dev,
1148 failed = dwc2_update_non_isoc_urb_state_ddma(hsotg, chan, qtd, dma_desc,
1152 dwc2_host_complete(hsotg, qtd, urb->status);
1153 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1154 dev_vdbg(hsotg->dev, "failed=%1x xfer_done=%1x\n",
1166 dev_vdbg(hsotg->dev,
1172 dev_vdbg(hsotg->dev,
1179 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1191 static void dwc2_complete_non_isoc_xfer_ddma(struct dwc2_hsotg *hsotg,
1217 if (dwc2_process_non_isoc_desc(hsotg, chan, chnum, qtd,
1237 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, NULL);
1257 * @hsotg: The HCD state structure for the DWC OTG controller
1269 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
1278 dwc2_complete_isoc_xfer_ddma(hsotg, chan, halt_status);
1292 dwc2_host_complete(hsotg, qtd,
1294 dwc2_hcd_qtd_unlink_and_free(hsotg,
1300 dwc2_hc_halt(hsotg, chan, halt_status);
1301 dwc2_release_channel_ddma(hsotg, qh);
1302 dwc2_hcd_qh_unlink(hsotg, qh);
1306 &hsotg->periodic_sched_assigned);
1323 dwc2_complete_non_isoc_xfer_ddma(hsotg, chan, chnum,
1325 dwc2_release_channel_ddma(hsotg, qh);
1326 dwc2_hcd_qh_unlink(hsotg, qh);
1333 dwc2_hcd_qh_add(hsotg, qh);
1337 tr_type = dwc2_hcd_select_transactions(hsotg);
1345 dwc2_hcd_queue_transactions(hsotg, tr_type);