Lines Matching refs:hsotg
40 * @hsotg: Programming view of the DWC_otg controller
42 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
47 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
50 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
55 if (!hsotg->params.host_dma)
57 if (!hsotg->params.external_id_pin_ctl)
63 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
66 dwc2_writel(hsotg, intmsk, GINTMSK);
69 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
71 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
73 switch (hsotg->hw_params.arch) {
75 dev_err(hsotg->dev, "External DMA Mode not supported\n");
79 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
80 if (hsotg->params.ahbcfg != -1) {
82 ahbcfg |= hsotg->params.ahbcfg &
89 dev_dbg(hsotg->dev, "Slave Only Mode\n");
93 if (hsotg->params.host_dma)
96 hsotg->params.dma_desc_enable = false;
98 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
103 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
107 usbcfg = dwc2_readl(hsotg, GUSBCFG);
110 switch (hsotg->hw_params.op_mode) {
112 if (hsotg->params.otg_caps.hnp_support &&
113 hsotg->params.otg_caps.srp_support)
120 if (hsotg->params.otg_caps.srp_support)
131 dwc2_writel(hsotg, usbcfg, GUSBCFG);
134 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
136 if (hsotg->vbus_supply)
137 return regulator_enable(hsotg->vbus_supply);
142 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
144 if (hsotg->vbus_supply)
145 return regulator_disable(hsotg->vbus_supply);
153 * @hsotg: Programming view of DWC_otg controller
155 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
159 dev_dbg(hsotg->dev, "%s()\n", __func__);
162 dwc2_writel(hsotg, 0, GINTMSK);
163 dwc2_writel(hsotg, 0, HAINTMSK);
166 dwc2_enable_common_interrupts(hsotg);
169 intmsk = dwc2_readl(hsotg, GINTMSK);
171 dwc2_writel(hsotg, intmsk, GINTMSK);
177 * @hsotg: Programming view of DWC_otg controller
179 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
181 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
186 dwc2_writel(hsotg, intmsk, GINTMSK);
194 * @hsotg: Programming view of DWC_otg controller
196 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
198 struct dwc2_core_params *params = &hsotg->params;
199 struct dwc2_hw_params *hw = &hsotg->hw_params;
252 dev_err(hsotg->dev, "invalid fifo sizes\n");
255 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
257 struct dwc2_core_params *params = &hsotg->params;
263 dwc2_calculate_dynamic_fifo(hsotg);
266 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
267 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
271 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
272 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
273 dwc2_readl(hsotg, GRXFSIZ));
276 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
277 dwc2_readl(hsotg, GNPTXFSIZ));
282 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
283 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
284 dwc2_readl(hsotg, GNPTXFSIZ));
287 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
288 dwc2_readl(hsotg, HPTXFSIZ));
294 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
295 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
296 dwc2_readl(hsotg, HPTXFSIZ));
298 if (hsotg->params.en_multiple_tx_fifo &&
299 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
305 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
312 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
320 * @hsotg: Programming view of DWC_otg controller
326 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
332 usbcfg = dwc2_readl(hsotg, GUSBCFG);
333 hprt0 = dwc2_readl(hsotg, HPRT0);
338 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
351 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
354 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
369 * @hsotg: Programming view of DWC_otg controller
373 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
385 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
388 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
394 * @hsotg: Programming view of DWC_otg controller
402 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
406 int num_channels = hsotg->params.host_channels;
417 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
418 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
419 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
420 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
422 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
423 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
425 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
427 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
429 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
430 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
431 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
432 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
433 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
434 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
435 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
437 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
438 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
439 dev_dbg(hsotg->dev, " NP inactive sched:\n");
440 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
442 dev_dbg(hsotg->dev, " %p\n", qh);
443 dev_dbg(hsotg->dev, " NP waiting sched:\n");
444 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
446 dev_dbg(hsotg->dev, " %p\n", qh);
447 dev_dbg(hsotg->dev, " NP active sched:\n");
448 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
450 dev_dbg(hsotg->dev, " %p\n", qh);
451 dev_dbg(hsotg->dev, " Channels:\n");
453 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
455 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
462 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
464 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
466 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
470 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
472 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
477 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
495 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
503 dev_vdbg(hsotg->dev, "control/bulk\n");
531 dev_vdbg(hsotg->dev, "intr\n");
553 dev_vdbg(hsotg->dev, "isoc\n");
564 dev_err(hsotg->dev, "## Unknown EP type ##\n");
568 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
570 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
573 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
582 if (!hsotg->params.dma_desc_enable) {
584 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
588 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
596 dev_vdbg(hsotg->dev, "setting ACK\n");
605 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
607 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
610 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
615 if (hsotg->params.host_dma) {
617 dev_vdbg(hsotg->dev, "DMA enabled\n");
618 dwc2_hc_enable_dma_ints(hsotg, chan);
621 dev_vdbg(hsotg->dev, "DMA disabled\n");
622 dwc2_hc_enable_slave_ints(hsotg, chan);
626 intmsk = dwc2_readl(hsotg, HAINTMSK);
628 dwc2_writel(hsotg, intmsk, HAINTMSK);
630 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
633 intmsk = dwc2_readl(hsotg, GINTMSK);
635 dwc2_writel(hsotg, intmsk, GINTMSK);
637 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
644 * @hsotg: Programming view of DWC_otg controller
651 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
659 dev_vdbg(hsotg->dev, "%s()\n", __func__);
664 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
667 dwc2_hc_enable_ints(hsotg, chan);
681 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
683 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
686 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
688 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
690 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
692 dev_vdbg(hsotg->dev, " Is In: %d\n",
694 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
696 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
698 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
705 dev_vdbg(hsotg->dev,
718 dev_vdbg(hsotg->dev, " comp split %d\n",
720 dev_vdbg(hsotg->dev, " xact pos %d\n",
722 dev_vdbg(hsotg->dev, " hub addr %d\n",
724 dev_vdbg(hsotg->dev, " hub port %d\n",
726 dev_vdbg(hsotg->dev, " is_in %d\n",
728 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
730 dev_vdbg(hsotg->dev, " xferlen %d\n",
735 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
741 * @hsotg: Controller register interface
766 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
772 dev_vdbg(hsotg->dev, "%s()\n", __func__);
780 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
781 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
785 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
792 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
804 dev_vdbg(hsotg->dev, "dequeue/error\n");
805 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
812 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
821 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
843 dev_vdbg(hsotg->dev,
849 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
853 if (!hsotg->params.dma_desc_enable) {
855 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
859 dev_dbg(hsotg->dev, "desc DMA enabled\n");
863 if (!hsotg->params.host_dma) {
865 dev_vdbg(hsotg->dev, "DMA not enabled\n");
871 dev_vdbg(hsotg->dev, "control/bulk\n");
872 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
874 dev_vdbg(hsotg->dev, "Disabling channel\n");
879 dev_vdbg(hsotg->dev, "isoc/intr\n");
880 hptxsts = dwc2_readl(hsotg, HPTXSTS);
882 hsotg->queuing_high_bandwidth) {
884 dev_vdbg(hsotg->dev, "Disabling channel\n");
890 dev_vdbg(hsotg->dev, "DMA enabled\n");
893 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
898 dev_vdbg(hsotg->dev, "Channel enabled\n");
903 dev_vdbg(hsotg->dev, "Channel disabled\n");
908 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
910 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
912 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
914 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
916 dev_vdbg(hsotg->dev, " halt_status: %d\n",
924 * @hsotg: Programming view of DWC_otg controller
930 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
942 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
945 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
952 * @hsotg: Programming view of DWC_otg controller
958 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
999 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1002 (hsotg->params.host_perio_tx_fifo_size -
1018 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1031 dwc2_sch_vdbg(hsotg,
1083 * @hsotg: Programming view of DWC_otg controller
1093 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1103 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1116 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1122 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1133 * @hsotg: Programming view of DWC_otg controller
1139 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1146 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1151 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1153 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1156 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1163 * @hsotg: Programming view of DWC_otg controller
1192 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1195 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1196 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1203 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1206 if (!hsotg->params.host_dma) {
1208 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1209 dwc2_hc_do_ping(hsotg, chan);
1215 dev_vdbg(hsotg->dev, "ping, DMA\n");
1222 dev_vdbg(hsotg->dev, "split\n");
1247 dev_vdbg(hsotg->dev, "no split\n");
1317 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1319 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1322 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1324 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1327 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1330 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1335 if (hsotg->params.host_dma) {
1340 dev_vdbg(hsotg->dev, "align_buf\n");
1345 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1348 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1354 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1357 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1360 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1363 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1366 dev_warn(hsotg->dev,
1375 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1379 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1381 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1387 if (!hsotg->params.host_dma &&
1390 dwc2_hc_write_packet(hsotg, chan);
1397 * @hsotg: Programming view of DWC_otg controller
1407 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1430 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1432 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1434 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1437 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1439 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1442 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1445 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1448 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1454 dev_warn(hsotg->dev,
1463 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1467 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1469 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1480 * @hsotg: Programming view of DWC_otg controller
1496 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1500 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1524 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1526 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1530 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1532 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1542 u32 hcchar = dwc2_readl(hsotg,
1545 dwc2_hc_set_even_odd_frame(hsotg, chan,
1550 dwc2_hc_write_packet(hsotg, chan);
1570 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1579 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1580 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1585 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1596 spin_lock_irqsave(&hsotg->lock, flags);
1599 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1602 dwc2_hcd_qh_unlink(hsotg, qh);
1607 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1612 spin_unlock_irqrestore(&hsotg->lock, flags);
1613 dwc2_hcd_qh_free(hsotg, qh);
1614 spin_lock_irqsave(&hsotg->lock, flags);
1617 spin_unlock_irqrestore(&hsotg->lock, flags);
1628 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1630 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1631 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1632 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1633 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1634 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1635 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1636 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1642 * @hsotg: Pointer to struct dwc2_hsotg
1644 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1648 if (hsotg->op_state == OTG_STATE_B_HOST) {
1654 hprt0 = dwc2_read_hprt0(hsotg);
1656 dwc2_writel(hsotg, hprt0, HPRT0);
1659 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1664 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1666 int num_channels = hsotg->params.host_channels;
1671 if (!hsotg->params.host_dma) {
1674 channel = hsotg->hc_ptr_array[i];
1677 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1681 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1687 channel = hsotg->hc_ptr_array[i];
1690 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1694 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1697 dwc2_hc_cleanup(hsotg, channel);
1698 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1707 if (hsotg->params.uframe_sched) {
1708 hsotg->available_host_channels =
1709 hsotg->params.host_channels;
1711 hsotg->non_periodic_channels = 0;
1712 hsotg->periodic_channels = 0;
1719 * @hsotg: Pointer to struct dwc2_hsotg
1723 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1725 if (hsotg->lx_state != DWC2_L0)
1726 usb_hcd_resume_root_hub(hsotg->priv);
1728 hsotg->flags.b.port_connect_status_change = 1;
1729 hsotg->flags.b.port_connect_status = 1;
1735 * @hsotg: Pointer to struct dwc2_hsotg
1740 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1746 hsotg->flags.b.port_connect_status_change = 1;
1747 hsotg->flags.b.port_connect_status = 0;
1754 intr = dwc2_readl(hsotg, GINTMSK);
1756 dwc2_writel(hsotg, intr, GINTMSK);
1758 dwc2_writel(hsotg, intr, GINTSTS);
1765 if (dwc2_is_device_mode(hsotg)) {
1766 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1767 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1768 dwc2_writel(hsotg, 0, HPRT0);
1771 dwc2_disable_host_interrupts(hsotg);
1775 dwc2_kill_all_urbs(hsotg);
1777 if (dwc2_is_host_mode(hsotg))
1779 dwc2_hcd_cleanup_channels(hsotg);
1781 dwc2_host_disconnect(hsotg);
1796 hprt0 = dwc2_readl(hsotg, HPRT0);
1798 dwc2_hcd_connect(hsotg);
1805 * @hsotg: Pointer to struct dwc2_hsotg
1807 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1809 if (hsotg->bus_suspended) {
1810 hsotg->flags.b.port_suspend_change = 1;
1811 usb_hcd_resume_root_hub(hsotg->priv);
1814 if (hsotg->lx_state == DWC2_L1)
1815 hsotg->flags.b.port_l1_change = 1;
1821 * @hsotg: Pointer to struct dwc2_hsotg
1825 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1827 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1836 dwc2_disable_host_interrupts(hsotg);
1839 dev_dbg(hsotg->dev, "PortPower off\n");
1840 dwc2_writel(hsotg, 0, HPRT0);
1844 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
1852 if (!hsotg->flags.b.port_connect_status) {
1854 dev_err(hsotg->dev, "Not connected\n");
1858 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1862 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
1863 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
1864 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
1875 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
1877 dev_err(hsotg->dev,
1883 intr_mask = dwc2_readl(hsotg, GINTMSK);
1895 tr_type = dwc2_hcd_select_transactions(hsotg);
1897 dwc2_hcd_queue_transactions(hsotg, tr_type);
1904 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
1912 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
1918 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
1925 dwc2_dump_channel_info(hsotg, qh->channel);
1928 if (hsotg->flags.b.port_connect_status)
1936 dwc2_hc_halt(hsotg, qh->channel,
1944 if (!hsotg->params.dma_desc_enable) {
1947 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1949 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
1952 dwc2_hcd_qh_unlink(hsotg, qh);
1955 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1962 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
1970 spin_lock_irqsave(&hsotg->lock, flags);
1980 dev_err(hsotg->dev,
1986 spin_unlock_irqrestore(&hsotg->lock, flags);
1988 spin_lock_irqsave(&hsotg->lock, flags);
1996 dwc2_hcd_qh_unlink(hsotg, qh);
2000 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2007 spin_unlock_irqrestore(&hsotg->lock, flags);
2009 dwc2_hcd_qh_free(hsotg, qh);
2015 spin_unlock_irqrestore(&hsotg->lock, flags);
2021 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2038 * @hsotg: Programming view of the DWC_otg controller
2041 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2046 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2048 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2052 if (hsotg->params.phy_ulpi_ext_vbus)
2057 if (hsotg->params.ts_dline)
2060 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2070 retval = dwc2_core_reset(hsotg, false);
2072 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2081 retval = dwc2_phy_init(hsotg, initial_setup);
2086 retval = dwc2_gahbcfg_init(hsotg);
2091 dwc2_gusbcfg_init(hsotg);
2094 otgctl = dwc2_readl(hsotg, GOTGCTL);
2096 dwc2_writel(hsotg, otgctl, GOTGCTL);
2099 hsotg->srp_success = 0;
2102 dwc2_enable_common_interrupts(hsotg);
2108 if (dwc2_is_host_mode(hsotg)) {
2109 dev_dbg(hsotg->dev, "Host Mode\n");
2110 hsotg->op_state = OTG_STATE_A_HOST;
2112 dev_dbg(hsotg->dev, "Device Mode\n");
2113 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2123 * @hsotg: Programming view of DWC_otg controller
2129 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2133 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2143 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2145 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2148 dwc2_writel(hsotg, 0, PCGCTL);
2151 dwc2_init_fs_ls_pclk_sel(hsotg);
2152 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2153 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2154 hcfg = dwc2_readl(hsotg, HCFG);
2156 dwc2_writel(hsotg, hcfg, HCFG);
2164 if (hsotg->params.reload_ctl) {
2165 hfir = dwc2_readl(hsotg, HFIR);
2167 dwc2_writel(hsotg, hfir, HFIR);
2170 if (hsotg->params.dma_desc_enable) {
2171 u32 op_mode = hsotg->hw_params.op_mode;
2173 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2174 !hsotg->hw_params.dma_desc_enable ||
2178 dev_err(hsotg->dev,
2180 dev_err(hsotg->dev,
2182 hsotg->params.dma_desc_enable = false;
2184 hcfg = dwc2_readl(hsotg, HCFG);
2186 dwc2_writel(hsotg, hcfg, HCFG);
2191 dwc2_config_fifos(hsotg);
2195 otgctl = dwc2_readl(hsotg, GOTGCTL);
2197 dwc2_writel(hsotg, otgctl, GOTGCTL);
2200 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2201 dwc2_flush_rx_fifo(hsotg);
2204 otgctl = dwc2_readl(hsotg, GOTGCTL);
2206 dwc2_writel(hsotg, otgctl, GOTGCTL);
2208 if (!hsotg->params.dma_desc_enable) {
2213 num_channels = hsotg->params.host_channels;
2215 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2220 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2226 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2230 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2231 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2234 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2237 dev_warn(hsotg->dev,
2246 dwc2_enable_acg(hsotg);
2249 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2250 if (hsotg->op_state == OTG_STATE_A_HOST) {
2251 u32 hprt0 = dwc2_read_hprt0(hsotg);
2253 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2257 dwc2_writel(hsotg, hprt0, HPRT0);
2261 dwc2_enable_host_interrupts(hsotg);
2269 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2275 hsotg->flags.d32 = 0;
2276 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2278 if (hsotg->params.uframe_sched) {
2279 hsotg->available_host_channels =
2280 hsotg->params.host_channels;
2282 hsotg->non_periodic_channels = 0;
2283 hsotg->periodic_channels = 0;
2290 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2294 num_channels = hsotg->params.host_channels;
2296 chan = hsotg->hc_ptr_array[i];
2297 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2298 dwc2_hc_cleanup(hsotg, chan);
2302 dwc2_core_host_init(hsotg);
2305 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2314 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2319 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2332 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2336 if (hsotg->params.host_dma)
2344 dev_vdbg(hsotg->dev, " Control data transaction\n");
2353 dev_vdbg(hsotg->dev, " Control status transaction\n");
2363 if (hsotg->params.host_dma)
2364 chan->xfer_dma = hsotg->status_buf_dma;
2366 chan->xfer_buf = hsotg->status_buf;
2381 if (hsotg->params.dma_desc_enable)
2387 if (hsotg->params.host_dma) {
2409 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2413 if (!hsotg->unaligned_cache ||
2418 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2424 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2428 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2429 dev_err(hsotg->dev, "can't map align_buf\n");
2540 * @hsotg: The HCD state structure
2544 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2551 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2554 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2558 if (list_empty(&hsotg->free_hc_list)) {
2559 dev_dbg(hsotg->dev, "No free channel to assign\n");
2563 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2610 if (hsotg->params.host_dma)
2620 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2625 dwc2_hc_init_xfer(hsotg, chan, qtd);
2628 if (hsotg->params.host_dma && qh->do_split &&
2630 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2631 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2632 dev_err(hsotg->dev,
2638 &hsotg->free_hc_list);
2648 WARN_ON_ONCE(hsotg->params.host_dma &&
2661 if (hsotg->params.dma_desc_enable) {
2666 dwc2_hc_init(hsotg, chan);
2677 * @hsotg: The HCD state structure
2682 struct dwc2_hsotg *hsotg)
2690 dev_vdbg(hsotg->dev, " Select Transactions\n");
2694 qh_ptr = hsotg->periodic_sched_ready.next;
2695 while (qh_ptr != &hsotg->periodic_sched_ready) {
2696 if (list_empty(&hsotg->free_hc_list))
2698 if (hsotg->params.uframe_sched) {
2699 if (hsotg->available_host_channels <= 1)
2701 hsotg->available_host_channels--;
2704 if (dwc2_assign_and_init_hc(hsotg, qh))
2713 &hsotg->periodic_sched_assigned);
2722 num_channels = hsotg->params.host_channels;
2723 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2724 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2725 if (!hsotg->params.uframe_sched &&
2726 hsotg->non_periodic_channels >= num_channels -
2727 hsotg->periodic_channels)
2729 if (list_empty(&hsotg->free_hc_list))
2732 if (hsotg->params.uframe_sched) {
2733 if (hsotg->available_host_channels < 1)
2735 hsotg->available_host_channels--;
2738 if (dwc2_assign_and_init_hc(hsotg, qh))
2747 &hsotg->non_periodic_sched_active);
2754 if (!hsotg->params.uframe_sched)
2755 hsotg->non_periodic_channels++;
2765 * @hsotg: The HCD state structure
2782 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2791 &hsotg->split_order);
2793 if (hsotg->params.host_dma && chan->qh) {
2794 if (hsotg->params.dma_desc_enable) {
2797 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2801 dwc2_hc_start_transfer(hsotg, chan);
2807 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2810 dwc2_hc_start_transfer(hsotg, chan);
2815 dwc2_hc_start_transfer(hsotg, chan);
2818 retval = dwc2_hc_continue_transfer(hsotg, chan);
2825 dwc2_hc_start_transfer(hsotg, chan);
2828 retval = dwc2_hc_continue_transfer(hsotg, chan);
2844 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2857 if (list_empty(&hsotg->periodic_sched_assigned))
2861 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2863 tx_status = dwc2_readl(hsotg, HPTXSTS);
2870 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2872 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2876 qh_ptr = hsotg->periodic_sched_assigned.next;
2877 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2878 tx_status = dwc2_readl(hsotg, HPTXSTS);
2903 if (!hsotg->params.host_dma &&
2905 hsotg->queuing_high_bandwidth = 1;
2909 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2922 if (hsotg->params.host_dma || status == 0 ||
2930 &hsotg->periodic_sched_queued);
2933 hsotg->queuing_high_bandwidth = 0;
2939 (!hsotg->params.host_dma &&
2940 !list_empty(&hsotg->periodic_sched_assigned))) {
2948 gintmsk = dwc2_readl(hsotg, GINTMSK);
2951 dwc2_writel(hsotg, gintmsk, GINTMSK);
2961 gintmsk = dwc2_readl(hsotg, GINTMSK);
2964 dwc2_writel(hsotg, gintmsk, GINTMSK);
2978 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
2991 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
2993 tx_status = dwc2_readl(hsotg, GNPTXSTS);
2998 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3000 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3007 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3008 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3009 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3016 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3019 if (!hsotg->params.host_dma && qspcavail == 0) {
3024 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3035 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3045 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3046 if (hsotg->non_periodic_qh_ptr ==
3047 &hsotg->non_periodic_sched_active)
3048 hsotg->non_periodic_qh_ptr =
3049 hsotg->non_periodic_qh_ptr->next;
3050 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3052 if (!hsotg->params.host_dma) {
3053 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3058 dev_vdbg(hsotg->dev,
3061 dev_vdbg(hsotg->dev,
3073 gintmsk = dwc2_readl(hsotg, GINTMSK);
3075 dwc2_writel(hsotg, gintmsk, GINTMSK);
3084 gintmsk = dwc2_readl(hsotg, GINTMSK);
3086 dwc2_writel(hsotg, gintmsk, GINTMSK);
3096 * @hsotg: The HCD state structure
3102 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3106 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3111 dwc2_process_periodic_channels(hsotg);
3116 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3117 dwc2_process_non_periodic_channels(hsotg);
3123 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3126 dwc2_writel(hsotg, gintmsk, GINTMSK);
3133 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3139 dev_dbg(hsotg->dev, "%s()\n", __func__);
3141 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3142 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3143 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3148 dwc2_vbus_supply_exit(hsotg);
3150 dev_dbg(hsotg->dev, "connId B\n");
3151 if (hsotg->bus_suspended) {
3152 dev_info(hsotg->dev,
3154 dwc2_port_resume(hsotg);
3156 while (!dwc2_is_device_mode(hsotg)) {
3157 dev_info(hsotg->dev,
3159 dwc2_is_host_mode(hsotg) ? "Host" :
3167 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3174 dev_err(hsotg->dev,
3182 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3183 dwc2_exit_partial_power_down(hsotg, 0, false);
3185 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3186 dwc2_core_init(hsotg, false);
3187 dwc2_enable_global_interrupts(hsotg);
3188 spin_lock_irqsave(&hsotg->lock, flags);
3189 dwc2_hsotg_core_init_disconnected(hsotg, false);
3190 spin_unlock_irqrestore(&hsotg->lock, flags);
3192 dwc2_enable_acg(hsotg);
3193 dwc2_hsotg_core_connect(hsotg);
3197 dev_dbg(hsotg->dev, "connId A\n");
3198 while (!dwc2_is_host_mode(hsotg)) {
3199 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3200 dwc2_is_host_mode(hsotg) ?
3207 dev_err(hsotg->dev,
3210 spin_lock_irqsave(&hsotg->lock, flags);
3211 dwc2_hsotg_disconnect(hsotg);
3212 spin_unlock_irqrestore(&hsotg->lock, flags);
3214 hsotg->op_state = OTG_STATE_A_HOST;
3216 dwc2_core_init(hsotg, false);
3217 dwc2_enable_global_interrupts(hsotg);
3218 dwc2_hcd_start(hsotg);
3224 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3227 dev_dbg(hsotg->dev, "%s()\n", __func__);
3233 hprt0 = dwc2_read_hprt0(hsotg);
3234 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3236 dwc2_writel(hsotg, hprt0, HPRT0);
3237 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3238 dwc2_readl(hsotg, HPRT0));
3240 dwc2_hcd_rem_wakeup(hsotg);
3241 hsotg->bus_suspended = false;
3244 hsotg->lx_state = DWC2_L0;
3247 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3249 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3257 * @hsotg: Programming view of the DWC_otg controller
3265 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3272 dev_dbg(hsotg->dev, "%s()\n", __func__);
3274 spin_lock_irqsave(&hsotg->lock, flags);
3276 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3277 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3279 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3280 hsotg->op_state = OTG_STATE_A_SUSPEND;
3283 switch (hsotg->params.power_down) {
3285 ret = dwc2_enter_partial_power_down(hsotg);
3287 dev_err(hsotg->dev,
3297 spin_unlock_irqrestore(&hsotg->lock, flags);
3298 ret = dwc2_enter_hibernation(hsotg, 1);
3300 dev_err(hsotg->dev, "enter hibernation failed.\n");
3301 spin_lock_irqsave(&hsotg->lock, flags);
3308 if (!hsotg->params.no_clock_gating)
3309 dwc2_host_enter_clock_gating(hsotg);
3314 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3315 pcgctl = dwc2_readl(hsotg, PCGCTL);
3317 dwc2_writel(hsotg, pcgctl, PCGCTL);
3319 spin_unlock_irqrestore(&hsotg->lock, flags);
3323 spin_unlock_irqrestore(&hsotg->lock, flags);
3332 * @hsotg: Programming view of the DWC_otg controller
3339 int dwc2_port_resume(struct dwc2_hsotg *hsotg)
3344 spin_lock_irqsave(&hsotg->lock, flags);
3346 switch (hsotg->params.power_down) {
3348 ret = dwc2_exit_partial_power_down(hsotg, 0, true);
3350 dev_err(hsotg->dev,
3355 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
3357 dev_err(hsotg->dev, "exit hibernation failed.\n");
3364 spin_unlock_irqrestore(&hsotg->lock, flags);
3365 dwc2_host_exit_clock_gating(hsotg, 0);
3366 spin_lock_irqsave(&hsotg->lock, flags);
3370 spin_unlock_irqrestore(&hsotg->lock, flags);
3376 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3389 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3399 dev_err(hsotg->dev,
3411 dev_dbg(hsotg->dev,
3413 hprt0 = dwc2_read_hprt0(hsotg);
3415 dwc2_writel(hsotg, hprt0, HPRT0);
3419 dev_dbg(hsotg->dev,
3422 if (hsotg->bus_suspended)
3423 retval = dwc2_port_resume(hsotg);
3427 dev_dbg(hsotg->dev,
3429 hprt0 = dwc2_read_hprt0(hsotg);
3432 dwc2_writel(hsotg, hprt0, HPRT0);
3434 dwc2_vbus_supply_exit(hsotg);
3438 dev_dbg(hsotg->dev,
3447 dev_dbg(hsotg->dev,
3449 hsotg->flags.b.port_connect_status_change = 0;
3454 dev_dbg(hsotg->dev,
3456 hsotg->flags.b.port_reset_change = 0;
3464 dev_dbg(hsotg->dev,
3466 hsotg->flags.b.port_enable_change = 0;
3475 dev_dbg(hsotg->dev,
3477 hsotg->flags.b.port_suspend_change = 0;
3481 dev_dbg(hsotg->dev,
3483 hsotg->flags.b.port_l1_change = 0;
3487 dev_dbg(hsotg->dev,
3489 hsotg->flags.b.port_over_current_change = 0;
3494 dev_err(hsotg->dev,
3501 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3516 dev_dbg(hsotg->dev, "GetHubStatus\n");
3521 dev_vdbg(hsotg->dev,
3523 hsotg->flags.d32);
3528 if (hsotg->flags.b.port_connect_status_change)
3530 if (hsotg->flags.b.port_enable_change)
3532 if (hsotg->flags.b.port_suspend_change)
3534 if (hsotg->flags.b.port_l1_change)
3536 if (hsotg->flags.b.port_reset_change)
3538 if (hsotg->flags.b.port_over_current_change) {
3539 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3543 if (!hsotg->flags.b.port_connect_status) {
3555 hprt0 = dwc2_readl(hsotg, HPRT0);
3556 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3581 if (hsotg->params.dma_desc_fs_enable) {
3586 if (hsotg->new_connection &&
3594 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3595 hsotg->params.dma_desc_enable = true;
3596 hcfg = dwc2_readl(hsotg, HCFG);
3598 dwc2_writel(hsotg, hcfg, HCFG);
3599 hsotg->new_connection = false;
3603 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3608 dev_dbg(hsotg->dev, "SetHubFeature\n");
3613 dev_dbg(hsotg->dev, "SetPortFeature\n");
3617 if (!hsotg->flags.b.port_connect_status) {
3630 dev_dbg(hsotg->dev,
3632 if (windex != hsotg->otg_port)
3634 if (!hsotg->bus_suspended)
3635 retval = dwc2_port_suspend(hsotg, windex);
3639 dev_dbg(hsotg->dev,
3641 hprt0 = dwc2_read_hprt0(hsotg);
3644 dwc2_writel(hsotg, hprt0, HPRT0);
3646 dwc2_vbus_supply_init(hsotg);
3650 dev_dbg(hsotg->dev,
3653 hprt0 = dwc2_read_hprt0(hsotg);
3655 if (hsotg->hibernated) {
3656 retval = dwc2_exit_hibernation(hsotg, 0, 1, 1);
3658 dev_err(hsotg->dev,
3662 if (hsotg->in_ppd) {
3663 retval = dwc2_exit_partial_power_down(hsotg, 1,
3666 dev_err(hsotg->dev,
3670 if (hsotg->params.power_down ==
3671 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
3672 dwc2_host_exit_clock_gating(hsotg, 0);
3674 pcgctl = dwc2_readl(hsotg, PCGCTL);
3676 dwc2_writel(hsotg, pcgctl, PCGCTL);
3678 dwc2_writel(hsotg, 0, PCGCTL);
3680 hprt0 = dwc2_read_hprt0(hsotg);
3690 if (!dwc2_hcd_is_b_host(hsotg)) {
3692 dev_dbg(hsotg->dev,
3694 dwc2_writel(hsotg, hprt0, HPRT0);
3696 dwc2_vbus_supply_init(hsotg);
3702 dwc2_writel(hsotg, hprt0, HPRT0);
3703 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3707 dev_dbg(hsotg->dev,
3713 hprt0 = dwc2_read_hprt0(hsotg);
3714 dev_dbg(hsotg->dev,
3718 dwc2_writel(hsotg, hprt0, HPRT0);
3723 dev_err(hsotg->dev,
3733 dev_dbg(hsotg->dev,
3742 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3749 retval = (hsotg->flags.b.port_connect_status_change ||
3750 hsotg->flags.b.port_reset_change ||
3751 hsotg->flags.b.port_enable_change ||
3752 hsotg->flags.b.port_suspend_change ||
3753 hsotg->flags.b.port_over_current_change);
3756 dev_dbg(hsotg->dev,
3758 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3759 hsotg->flags.b.port_connect_status_change);
3760 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3761 hsotg->flags.b.port_reset_change);
3762 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3763 hsotg->flags.b.port_enable_change);
3764 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3765 hsotg->flags.b.port_suspend_change);
3766 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3767 hsotg->flags.b.port_over_current_change);
3773 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3775 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3778 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3784 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3786 u32 hprt = dwc2_readl(hsotg, HPRT0);
3787 u32 hfir = dwc2_readl(hsotg, HFIR);
3788 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3813 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3815 return hsotg->op_state == OTG_STATE_B_HOST;
3818 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3830 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3838 dev_vdbg(hsotg->dev,
3853 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3864 num_channels = hsotg->params.host_channels;
3865 dev_dbg(hsotg->dev, "\n");
3866 dev_dbg(hsotg->dev,
3868 dev_dbg(hsotg->dev, "HCD State:\n");
3869 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3872 chan = hsotg->hc_ptr_array[i];
3873 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3874 dev_dbg(hsotg->dev,
3877 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3878 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3879 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3880 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3882 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3883 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3885 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3886 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3888 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3889 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3890 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3892 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3894 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3895 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3896 dev_dbg(hsotg->dev, " complete_split: %d\n",
3898 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3899 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3900 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3901 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3902 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3907 hfnum = dwc2_readl(hsotg, HFNUM);
3908 hcchar = dwc2_readl(hsotg, HCCHAR(i));
3909 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
3910 hcint = dwc2_readl(hsotg, HCINT(i));
3911 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
3912 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3913 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3914 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3915 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3916 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3926 dev_dbg(hsotg->dev, " URB Info:\n");
3927 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3930 dev_dbg(hsotg->dev,
3936 dev_dbg(hsotg->dev,
3940 dev_dbg(hsotg->dev,
3943 dev_dbg(hsotg->dev,
3946 dev_dbg(hsotg->dev,
3949 dev_dbg(hsotg->dev, " actual_length: %d\n",
3955 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3956 hsotg->non_periodic_channels);
3957 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3958 hsotg->periodic_channels);
3959 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
3960 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
3961 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
3963 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
3965 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
3966 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
3968 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
3970 dwc2_dump_global_registers(hsotg);
3971 dwc2_dump_host_registers(hsotg);
3972 dev_dbg(hsotg->dev,
3974 dev_dbg(hsotg->dev, "\n");
3979 struct dwc2_hsotg *hsotg;
3988 return p->hsotg;
4001 * @hsotg: The HCD state structure for the DWC OTG controller.
4011 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4056 * @hsotg: The HCD state structure for the DWC OTG controller.
4059 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4074 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4113 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4120 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4125 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4131 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4138 dev_vdbg(hsotg->dev,
4158 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4174 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4175 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4179 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4184 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4192 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4195 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4196 dwc2_host_start(hsotg);
4204 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4209 dev_dbg(hsotg->dev, "USB RESET function called\n");
4211 spin_lock_irqsave(&hsotg->lock, flags);
4213 hprt0 = dwc2_read_hprt0(hsotg);
4215 dwc2_writel(hsotg, hprt0, HPRT0);
4216 hsotg->flags.b.port_reset_change = 1;
4218 spin_unlock_irqrestore(&hsotg->lock, flags);
4223 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4227 ret = phy_reset(hsotg->phy);
4229 dev_warn(hsotg->dev, "PHY reset failed\n");
4245 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4251 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4253 spin_lock_irqsave(&hsotg->lock, flags);
4254 hsotg->lx_state = DWC2_L0;
4258 if (dwc2_is_device_mode(hsotg)) {
4259 spin_unlock_irqrestore(&hsotg->lock, flags);
4263 dwc2_hcd_reinit(hsotg);
4265 hprt0 = dwc2_read_hprt0(hsotg);
4269 spin_unlock_irqrestore(&hsotg->lock, flags);
4270 ret = dwc2_vbus_supply_init(hsotg);
4273 spin_lock_irqsave(&hsotg->lock, flags);
4278 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4283 spin_unlock_irqrestore(&hsotg->lock, flags);
4294 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4299 dwc2_disable_host_interrupts(hsotg);
4304 spin_lock_irqsave(&hsotg->lock, flags);
4305 hprt0 = dwc2_read_hprt0(hsotg);
4307 dwc2_hcd_disconnect(hsotg, true);
4308 dwc2_hcd_stop(hsotg);
4309 hsotg->lx_state = DWC2_L3;
4312 spin_unlock_irqrestore(&hsotg->lock, flags);
4316 dwc2_vbus_supply_exit(hsotg);
4323 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4327 spin_lock_irqsave(&hsotg->lock, flags);
4329 if (dwc2_is_device_mode(hsotg))
4332 if (hsotg->lx_state != DWC2_L0)
4338 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4341 if (hsotg->bus_suspended)
4344 if (hsotg->flags.b.port_connect_status == 0)
4347 switch (hsotg->params.power_down) {
4350 ret = dwc2_enter_partial_power_down(hsotg);
4352 dev_err(hsotg->dev,
4359 spin_unlock_irqrestore(&hsotg->lock, flags);
4360 ret = dwc2_enter_hibernation(hsotg, 1);
4362 dev_err(hsotg->dev, "enter hibernation failed\n");
4363 spin_lock_irqsave(&hsotg->lock, flags);
4373 if (!hsotg->params.no_clock_gating) {
4374 dwc2_host_enter_clock_gating(hsotg);
4384 spin_unlock_irqrestore(&hsotg->lock, flags);
4385 dwc2_vbus_supply_exit(hsotg);
4386 spin_lock_irqsave(&hsotg->lock, flags);
4389 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4390 spin_unlock_irqrestore(&hsotg->lock, flags);
4391 usb_phy_set_suspend(hsotg->uphy, true);
4392 spin_lock_irqsave(&hsotg->lock, flags);
4396 hsotg->lx_state = DWC2_L2;
4398 spin_unlock_irqrestore(&hsotg->lock, flags);
4405 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4410 spin_lock_irqsave(&hsotg->lock, flags);
4412 if (dwc2_is_device_mode(hsotg))
4415 if (hsotg->lx_state != DWC2_L2)
4418 hprt0 = dwc2_read_hprt0(hsotg);
4426 hsotg->lx_state = DWC2_L0;
4430 switch (hsotg->params.power_down) {
4432 ret = dwc2_exit_partial_power_down(hsotg, 0, true);
4434 dev_err(hsotg->dev,
4443 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
4445 dev_err(hsotg->dev, "exit hibernation failed.\n");
4458 spin_unlock_irqrestore(&hsotg->lock, flags);
4459 dwc2_host_exit_clock_gating(hsotg, 0);
4465 dwc2_core_init(hsotg, false);
4466 dwc2_enable_global_interrupts(hsotg);
4467 dwc2_hcd_reinit(hsotg);
4468 spin_lock_irqsave(&hsotg->lock, flags);
4477 hsotg->lx_state = DWC2_L0;
4482 hsotg->flags.b.port_suspend_change = 1;
4489 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4490 spin_unlock_irqrestore(&hsotg->lock, flags);
4491 usb_phy_set_suspend(hsotg->uphy, false);
4492 spin_lock_irqsave(&hsotg->lock, flags);
4496 spin_unlock_irqrestore(&hsotg->lock, flags);
4497 dwc2_vbus_supply_init(hsotg);
4501 spin_lock_irqsave(&hsotg->lock, flags);
4507 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4511 spin_unlock_irqrestore(&hsotg->lock, flags);
4513 spin_lock_irqsave(&hsotg->lock, flags);
4515 spin_unlock_irqrestore(&hsotg->lock, flags);
4523 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4525 return dwc2_hcd_get_frame_number(hsotg);
4532 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4536 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4537 dev_vdbg(hsotg->dev, " Device address: %d\n",
4539 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4558 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4577 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4578 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n",
4582 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4584 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4586 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4588 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4594 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4595 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4611 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4626 gr = &hsotg->gr_backup;
4629 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4633 if (hsotg->hibernated) {
4635 retval = dwc2_exit_hibernation(hsotg, 0, 0, 1);
4637 retval = dwc2_exit_hibernation(hsotg, 0, 0, 0);
4640 dev_err(hsotg->dev,
4644 if (hsotg->in_ppd) {
4645 retval = dwc2_exit_partial_power_down(hsotg, 0, true);
4647 dev_err(hsotg->dev,
4651 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
4652 hsotg->bus_suspended) {
4653 if (dwc2_is_device_mode(hsotg))
4654 dwc2_gadget_exit_clock_gating(hsotg, 0);
4656 dwc2_host_exit_clock_gating(hsotg, 0);
4664 spin_lock_irqsave(&hsotg->lock, flags);
4665 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4667 spin_unlock_irqrestore(&hsotg->lock, flags);
4685 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4690 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4700 dev_err(hsotg->dev,
4732 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4747 spin_lock_irqsave(&hsotg->lock, flags);
4752 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4758 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4762 spin_unlock_irqrestore(&hsotg->lock, flags);
4773 spin_unlock_irqrestore(&hsotg->lock, flags);
4780 dwc2_hcd_qh_unlink(hsotg, qh);
4784 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4785 dwc2_hcd_qh_free(hsotg, qh);
4799 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4803 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4806 spin_lock_irqsave(&hsotg->lock, flags);
4813 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4817 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4825 spin_unlock(&hsotg->lock);
4827 spin_lock(&hsotg->lock);
4829 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4830 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4832 spin_unlock_irqrestore(&hsotg->lock, flags);
4845 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4847 dev_dbg(hsotg->dev,
4850 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4861 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4864 dev_dbg(hsotg->dev,
4868 spin_lock_irqsave(&hsotg->lock, flags);
4869 dwc2_hcd_endpoint_reset(hsotg, ep);
4870 spin_unlock_irqrestore(&hsotg->lock, flags);
4882 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4884 return dwc2_handle_hcd_intr(hsotg);
4895 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4897 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4914 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4922 spin_lock_irqsave(&hsotg->lock, flags);
4925 if (hsotg->flags.b.port_connect_status)
4926 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4928 spin_unlock_irqrestore(&hsotg->lock, flags);
4937 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4939 if (hsotg->params.speed == speed)
4942 hsotg->params.speed = speed;
4943 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4948 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4950 if (!hsotg->params.change_speed_quirk)
4958 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4965 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4967 if (!hsotg->params.change_speed_quirk)
4971 dev_info(hsotg->dev, "Set speed to high-speed\n");
4979 dev_info(hsotg->dev, "Set speed to full-speed\n");
5017 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5023 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5026 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5027 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
5028 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5029 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5030 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5031 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5032 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5036 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5039 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5041 hsotg->hc_ptr_array[i] = NULL;
5046 if (hsotg->params.host_dma) {
5047 if (hsotg->status_buf) {
5048 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5049 hsotg->status_buf,
5050 hsotg->status_buf_dma);
5051 hsotg->status_buf = NULL;
5054 kfree(hsotg->status_buf);
5055 hsotg->status_buf = NULL;
5058 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
5062 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5063 dwc2_writel(hsotg, 0, GINTMSK);
5065 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5066 dctl = dwc2_readl(hsotg, DCTL);
5068 dwc2_writel(hsotg, dctl, DCTL);
5071 if (hsotg->wq_otg) {
5072 if (!cancel_work_sync(&hsotg->wf_otg))
5073 flush_workqueue(hsotg->wq_otg);
5074 destroy_workqueue(hsotg->wq_otg);
5077 cancel_work_sync(&hsotg->phy_reset_work);
5079 del_timer(&hsotg->wkp_timer);
5082 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5085 dwc2_disable_host_interrupts(hsotg);
5087 dwc2_hcd_free(hsotg);
5096 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5098 struct platform_device *pdev = to_platform_device(hsotg->dev);
5109 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5113 hcfg = dwc2_readl(hsotg, HCFG);
5114 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5117 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5118 sizeof(*hsotg->frame_num_array),
5120 if (!hsotg->frame_num_array)
5122 hsotg->last_frame_num_array =
5124 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5125 if (!hsotg->last_frame_num_array)
5128 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5131 if (hsotg->params.host_dma &&
5132 !hsotg->dev->dma_mask) {
5133 dev_warn(hsotg->dev,
5135 hsotg->params.host_dma = false;
5136 hsotg->params.dma_desc_enable = false;
5140 if (hsotg->params.host_dma) {
5141 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5142 dev_warn(hsotg->dev, "can't set DMA mask\n");
5143 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5144 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5147 if (hsotg->params.change_speed_quirk) {
5152 if (hsotg->params.host_dma)
5155 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5169 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5170 hsotg->priv = hcd;
5176 dwc2_disable_global_interrupts(hsotg);
5179 retval = dwc2_core_init(hsotg, true);
5185 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5186 if (!hsotg->wq_otg) {
5187 dev_err(hsotg->dev, "Failed to create workqueue\n");
5190 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5192 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5195 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5196 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5197 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5200 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5201 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5202 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5203 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5205 INIT_LIST_HEAD(&hsotg->split_order);
5211 INIT_LIST_HEAD(&hsotg->free_hc_list);
5212 num_channels = hsotg->params.host_channels;
5213 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5221 hsotg->hc_ptr_array[i] = channel;
5225 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5226 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5227 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
5235 if (hsotg->params.host_dma)
5236 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5238 &hsotg->status_buf_dma, GFP_KERNEL);
5240 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5243 if (!hsotg->status_buf)
5251 if (hsotg->params.dma_desc_enable ||
5252 hsotg->params.dma_desc_fs_enable) {
5253 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5257 if (!hsotg->desc_gen_cache) {
5258 dev_err(hsotg->dev,
5265 hsotg->params.dma_desc_enable = false;
5266 hsotg->params.dma_desc_fs_enable = false;
5269 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5272 if (!hsotg->desc_hsisoc_cache) {
5273 dev_err(hsotg->dev,
5276 kmem_cache_destroy(hsotg->desc_gen_cache);
5282 hsotg->params.dma_desc_enable = false;
5283 hsotg->params.dma_desc_fs_enable = false;
5287 if (hsotg->params.host_dma) {
5292 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5295 if (!hsotg->unaligned_cache)
5296 dev_err(hsotg->dev,
5300 hsotg->otg_port = 1;
5301 hsotg->frame_list = NULL;
5302 hsotg->frame_list_dma = 0;
5303 hsotg->periodic_qh_count = 0;
5306 hsotg->lx_state = DWC2_L3;
5308 hcd->self.otg_port = hsotg->otg_port;
5313 hcd->tpl_support = of_usb_host_tpl_support(hsotg->dev->of_node);
5315 if (!IS_ERR_OR_NULL(hsotg->uphy))
5316 otg_set_host(hsotg->uphy->otg, &hcd->self);
5323 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5329 dwc2_hcd_dump_state(hsotg);
5331 dwc2_enable_global_interrupts(hsotg);
5336 kmem_cache_destroy(hsotg->unaligned_cache);
5337 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5338 kmem_cache_destroy(hsotg->desc_gen_cache);
5340 dwc2_hcd_release(hsotg);
5346 kfree(hsotg->last_frame_num_array);
5347 kfree(hsotg->frame_num_array);
5350 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5358 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5362 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5364 hcd = dwc2_hsotg_to_hcd(hsotg);
5365 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5368 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5373 if (!IS_ERR_OR_NULL(hsotg->uphy))
5374 otg_set_host(hsotg->uphy->otg, NULL);
5377 hsotg->priv = NULL;
5379 kmem_cache_destroy(hsotg->unaligned_cache);
5380 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5381 kmem_cache_destroy(hsotg->desc_gen_cache);
5383 dwc2_hcd_release(hsotg);
5387 kfree(hsotg->last_frame_num_array);
5388 kfree(hsotg->frame_num_array);
5397 * @hsotg: Programming view of the DWC_otg controller
5399 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5404 dev_dbg(hsotg->dev, "%s\n", __func__);
5407 hr = &hsotg->hr_backup;
5408 hr->hcfg = dwc2_readl(hsotg, HCFG);
5409 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5410 for (i = 0; i < hsotg->params.host_channels; ++i)
5411 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5413 hr->hprt0 = dwc2_read_hprt0(hsotg);
5414 hr->hfir = dwc2_readl(hsotg, HFIR);
5415 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5426 * @hsotg: Programming view of the DWC_otg controller
5428 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5433 dev_dbg(hsotg->dev, "%s\n", __func__);
5436 hr = &hsotg->hr_backup;
5438 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5444 dwc2_writel(hsotg, hr->hcfg, HCFG);
5445 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5447 for (i = 0; i < hsotg->params.host_channels; ++i)
5448 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5450 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5451 dwc2_writel(hsotg, hr->hfir, HFIR);
5452 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5453 hsotg->frame_number = 0;
5461 * @hsotg: Programming view of the DWC_otg controller
5463 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5472 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5473 ret = dwc2_backup_global_registers(hsotg);
5475 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5479 ret = dwc2_backup_host_registers(hsotg);
5481 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5487 hprt0 = dwc2_readl(hsotg, HPRT0);
5490 dwc2_writel(hsotg, hprt0, HPRT0);
5493 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 5000))
5494 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5500 spin_lock_irqsave(&hsotg->lock, flags);
5501 hsotg->lx_state = DWC2_L2;
5503 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5507 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5509 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5512 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5514 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5518 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5520 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5523 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5525 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5530 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5532 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5536 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5540 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5544 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5546 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5550 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5552 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5554 hsotg->hibernated = 1;
5555 hsotg->bus_suspended = 1;
5556 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5557 spin_unlock_irqrestore(&hsotg->lock, flags);
5564 * @hsotg: Programming view of the DWC_otg controller
5573 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5582 gr = &hsotg->gr_backup;
5583 hr = &hsotg->hr_backup;
5585 dev_dbg(hsotg->dev,
5589 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5590 hsotg->hibernated = 0;
5600 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5603 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5605 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5609 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5610 dwc2_writel(hsotg, hr->hcfg, HCFG);
5613 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5615 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5622 dwc2_writel(hsotg, hprt0, HPRT0);
5631 dwc2_writel(hsotg, hprt0, HPRT0);
5636 dwc2_writel(hsotg, hprt0, HPRT0);
5639 dwc2_writel(hsotg, hprt0, HPRT0);
5644 dwc2_writel(hsotg, hprt0, HPRT0);
5647 hprt0 = dwc2_readl(hsotg, HPRT0);
5651 dwc2_writel(hsotg, hprt0, HPRT0);
5653 hprt0 = dwc2_readl(hsotg, HPRT0);
5656 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5659 ret = dwc2_restore_global_registers(hsotg);
5661 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5667 ret = dwc2_restore_host_registers(hsotg);
5669 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5675 dwc2_hcd_rem_wakeup(hsotg);
5681 hsotg->flags.b.port_connect_status_change = 1;
5684 hsotg->hibernated = 0;
5685 hsotg->bus_suspended = 0;
5686 hsotg->lx_state = DWC2_L0;
5687 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
5714 * @hsotg: Programming view of the DWC_otg controller
5720 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5726 dev_dbg(hsotg->dev, "Entering host partial power down started.\n");
5729 hprt0 = dwc2_read_hprt0(hsotg);
5731 dwc2_writel(hsotg, hprt0, HPRT0);
5735 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5736 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5739 ret = dwc2_backup_global_registers(hsotg);
5741 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5746 ret = dwc2_backup_host_registers(hsotg);
5748 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5757 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5760 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5763 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5767 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5771 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5774 hsotg->in_ppd = 1;
5775 hsotg->lx_state = DWC2_L2;
5776 hsotg->bus_suspended = true;
5778 dev_dbg(hsotg->dev, "Entering host partial power down completed.\n");
5787 * @hsotg: Programming view of the DWC_otg controller
5795 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5802 dev_dbg(hsotg->dev, "Exiting host partial power down started.\n");
5804 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5806 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5809 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5811 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5814 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5816 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5820 ret = dwc2_restore_global_registers(hsotg);
5822 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5827 ret = dwc2_restore_host_registers(hsotg);
5829 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5836 hprt0 = dwc2_read_hprt0(hsotg);
5839 dwc2_writel(hsotg, hprt0, HPRT0);
5844 hprt0 = dwc2_read_hprt0(hsotg);
5846 dwc2_writel(hsotg, hprt0, HPRT0);
5848 hsotg->bus_suspended = false;
5851 hprt0 = dwc2_read_hprt0(hsotg);
5853 dwc2_writel(hsotg, hprt0, HPRT0);
5856 dwc2_hcd_connect(hsotg);
5858 mod_timer(&hsotg->wkp_timer,
5863 hsotg->in_ppd = 0;
5864 hsotg->lx_state = DWC2_L0;
5866 dev_dbg(hsotg->dev, "Exiting host partial power down completed.\n");
5873 * @hsotg: Programming view of the DWC_otg controller
5877 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg)
5882 dev_dbg(hsotg->dev, "Entering host clock gating.\n");
5885 hprt0 = dwc2_read_hprt0(hsotg);
5887 dwc2_writel(hsotg, hprt0, HPRT0);
5890 pcgctl = dwc2_readl(hsotg, PCGCTL);
5892 dwc2_writel(hsotg, pcgctl, PCGCTL);
5896 pcgctl = dwc2_readl(hsotg, PCGCTL);
5898 dwc2_writel(hsotg, pcgctl, PCGCTL);
5901 hsotg->bus_suspended = true;
5902 hsotg->lx_state = DWC2_L2;
5908 * @hsotg: Programming view of the DWC_otg controller
5913 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5918 dev_dbg(hsotg->dev, "Exiting host clock gating.\n");
5921 pcgctl = dwc2_readl(hsotg, PCGCTL);
5923 dwc2_writel(hsotg, pcgctl, PCGCTL);
5927 pcgctl = dwc2_readl(hsotg, PCGCTL);
5929 dwc2_writel(hsotg, pcgctl, PCGCTL);
5933 hprt0 = dwc2_read_hprt0(hsotg);
5936 dwc2_writel(hsotg, hprt0, HPRT0);
5944 hprt0 = dwc2_read_hprt0(hsotg);
5946 dwc2_writel(hsotg, hprt0, HPRT0);
5948 hsotg->bus_suspended = false;
5949 hsotg->lx_state = DWC2_L0;
5951 mod_timer(&hsotg->wkp_timer,