Lines Matching defs:channel
217 * with n = number of host channel.
392 * dwc2_dump_channel_info() - Prints the state of a host channel
395 * @chan: Pointer to the channel to dump
422 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
579 * For Descriptor DMA mode core halts the channel on AHB error.
625 /* Enable the top level host channel interrupt */
632 /* Make sure host channel interrupts are enabled */
641 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
645 * @chan: Information needed to initialize the host channel
648 * Host channel interrupts that may need to be serviced while this transfer is
661 /* Clear old interrupt conditions for this host channel */
666 /* Enable channel interrupts required for this transfer */
739 * dwc2_hc_halt() - Attempts to halt a host channel
742 * @chan: Host channel to halt
743 * @halt_status: Reason for halting the channel
747 * controller halts the channel when the transfer is complete or a condition
752 * register of the specified channel to intiate the halt. If there is no free
754 * register to flush requests for this channel. In the latter case, sets a
755 * flag to indicate that the host channel needs to be halted when a request
763 * host channel and halts. The Channel Halted interrupt handler completes the
764 * deactivation of the host channel.
775 * In buffer DMA or external DMA mode channel can't be halted
777 * uframe/frame (in the worst case), the core generates a channel
778 * halted and disables the channel automatically.
797 * Disable all channel interrupts except Ch Halted. The QTD
799 * (in the case of URB_DEQUEUE), so the channel needs to be
816 * even if the channel was already halted for some other
824 * The channel is either already halted or it hasn't
828 * the channel again. In either Slave or DMA mode,
830 * to a channel, but not started yet when an URB is
831 * dequeued. Don't want to halt a channel that hasn't
839 * A halt has already been issued for this channel. This might
851 /* No need to set the bit in DDMA for disabling the channel */
852 /* TODO check it everywhere channel is disabled */
874 dev_vdbg(hsotg->dev, "Disabling channel\n");
884 dev_vdbg(hsotg->dev, "Disabling channel\n");
922 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
925 * @chan: Identifies the host channel to clean up
928 * channel is being released
939 * Clear channel interrupt enables and any unhandled channel interrupt
949 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
953 * @chan: Identifies the host channel to set up and its properties
954 * @hcchar: Current value of the HCCHAR register for the specified host channel
1084 * @chan: Information needed to initialize the host channel
1086 * This function should only be called in Slave mode. For a channel associated
1087 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1134 * @chan: Information needed to initialize the host channel
1137 * the HCTSIZ register, then the channel is enabled.
1161 * channel and starts the transfer
1164 * @chan: Information needed to initialize the host channel. The xfer_len value
1182 * register along with a packet count of 1 and the channel is enabled. This
1259 * programmed into a channel.)
1367 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1370 /* Set host channel enable after all other setup is complete */
1395 * host channel and starts the transfer in Descriptor DMA mode
1398 * @chan: Information needed to initialize the host channel
1405 * starts the transfer via enabling the channel.
1455 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1458 /* Set host channel enable after all other setup is complete */
1481 * @chan: Information needed to initialize the host channel
1486 * channel.
1504 /* SPLITs always queue just once per channel */
1521 * transfer completes, the extra requests for the channel will
1609 if (qh->channel && qh->channel->qh == qh)
1610 qh->channel->qh = NULL;
1667 struct dwc2_host_chan *channel;
1672 /* Flush out any channel requests in slave mode */
1674 channel = hsotg->hc_ptr_array[i];
1675 if (!list_empty(&channel->hc_list_entry))
1687 channel = hsotg->hc_ptr_array[i];
1688 if (!list_empty(&channel->hc_list_entry))
1692 /* Halt the channel */
1697 dwc2_hc_cleanup(hsotg, channel);
1698 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1700 * Added for Descriptor DMA to prevent channel double cleanup in
1704 channel->qh = NULL;
1752 * channel interrupts.
1924 if (urb_qtd->in_process && qh->channel) {
1925 dwc2_dump_channel_info(hsotg, qh->channel);
1927 /* The QTD is in process (it has been assigned to a channel) */
1931 * channel so it can be used for other transfers. If
1933 * written to halt the channel since the core is in
1936 dwc2_hc_halt(hsotg, qh->channel,
1950 qh->channel = NULL;
2004 if (qh->channel && qh->channel->qh == qh)
2005 qh->channel->qh = NULL;
2231 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2238 "Unable to clear enable on channel %d\n",
2287 * Put all channels in the free channel list and clean up channel
2537 * channel and initializes the host channel to perform the transactions. The
2538 * host channel is removed from the free list.
2542 * to a free host channel
2559 dev_dbg(hsotg->dev, "No free channel to assign\n");
2566 /* Remove host channel from free list */
2571 qh->channel = chan;
2634 /* Add channel back to free list */
2640 qh->channel = NULL;
2763 * a host channel associated with either a periodic or non-periodic transfer
2766 * @chan: Host channel descriptor associated with either a periodic or
2805 /* Don't queue a request if the channel has been halted */
2887 if (!qh->channel) {
2904 qh->channel->multi_count > 1)
2909 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2923 qh->channel->requests == qh->channel->multi_count) {
3026 if (!qh->channel)
3035 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
4769 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4770 qh->channel->qh = NULL;
5039 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5101 struct dwc2_host_chan *channel;
5208 * Create a host channel descriptor for each host channel implemented
5209 * in the controller. Initialize the channel descriptor array.
5216 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5217 if (!channel)
5219 channel->hc_num = i;
5220 INIT_LIST_HEAD(&channel->split_order_list_entry);
5221 hsotg->hc_ptr_array[i] = channel;