Lines Matching defs:ctrl
989 u32 ctrl;
1027 ctrl = dwc2_readl(hsotg, depctl);
1028 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1029 dwc2_writel(hsotg, ctrl, depctl);
1059 u32 ctrl;
1087 ctrl = dwc2_readl(hsotg, epctrl_reg);
1089 if (index && ctrl & DXEPCTL_STALL) {
1194 ctrl |= DXEPCTL_SETODDFR;
1196 ctrl |= DXEPCTL_SETEVENFR;
1198 ctrl |= DXEPCTL_CNAK;
1207 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1213 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1215 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1216 dwc2_writel(hsotg, ctrl, epctrl_reg);
1664 * @ctrl: USB control request
1667 struct usb_ctrlrequest *ctrl)
1682 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1697 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1708 if (le16_to_cpu(ctrl->wLength) != 2)
1768 * @ctrl: USB control request
1771 struct usb_ctrlrequest *ctrl)
1775 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1786 wValue = le16_to_cpu(ctrl->wValue);
1787 wIndex = le16_to_cpu(ctrl->wIndex);
1788 recip = ctrl->bRequestType & USB_RECIP_MASK;
1893 u32 ctrl;
1903 ctrl = dwc2_readl(hsotg, reg);
1904 ctrl |= DXEPCTL_STALL;
1905 ctrl |= DXEPCTL_CNAK;
1906 dwc2_writel(hsotg, ctrl, reg);
1910 ctrl, reg, dwc2_readl(hsotg, reg));
1922 * @ctrl: The control request received
1929 struct usb_ctrlrequest *ctrl)
1936 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1937 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1938 ctrl->wIndex, ctrl->wLength);
1940 if (ctrl->wLength == 0) {
1943 } else if (ctrl->bRequestType & USB_DIR_IN) {
1951 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1952 switch (ctrl->bRequest) {
1957 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1961 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1967 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1972 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1981 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
2069 u32 ctrl;
2094 ctrl = dwc2_readl(hsotg, epctl_reg);
2095 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2096 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2097 ctrl |= DXEPCTL_USBACTEP;
2098 dwc2_writel(hsotg, ctrl, epctl_reg);
2903 u32 ctrl;
2907 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2909 ctrl |= DXEPCTL_SETODDFR;
2911 ctrl |= DXEPCTL_SETEVENFR;
2913 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2957 u32 ctrl;
2990 u32 ctrl = dwc2_readl(hsotg,
2993 ctrl |= DXEPCTL_SETODDFR;
2995 ctrl |= DXEPCTL_SETEVENFR;
2997 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3004 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3005 if (ctrl & DXEPCTL_EPENA)
4072 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4241 u32 ctrl;
4257 ctrl = dwc2_readl(hsotg, epctrl_reg);
4259 if (ctrl & DXEPCTL_EPENA)
4262 ctrl &= ~DXEPCTL_EPENA;
4263 ctrl &= ~DXEPCTL_USBACTEP;
4264 ctrl |= DXEPCTL_SNAK;
4266 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4267 dwc2_writel(hsotg, ctrl, epctrl_reg);
5047 dev_err(dev, "failed to allocate ctrl req\n");