Lines Matching defs:value
102 static inline void cdns_imx_writel(struct cdns_imx *data, u32 offset, u32 value)
104 writel(value, data->noncore + offset);
117 u32 value;
123 ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value,
124 (value & CLK_VALID_COMPARE_BITS) == CLK_VALID_COMPARE_BITS,
131 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
132 value |= ALL_SW_RESET;
133 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
136 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
137 value = (value & ~MODE_STRAP_MASK) | OTG_MODE | OC_DISABLE;
138 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
140 value = cdns_imx_readl(data, USB3_INT_REG);
141 value |= HOST_INT1_EN | DEV_INT_EN;
142 cdns_imx_writel(data, USB3_INT_REG, value);
144 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
145 value &= ~ALL_SW_RESET;
146 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
237 u32 value;
239 value = cdns_imx_readl(data, USB3_INT_REG);
241 value |= OTG_WAKEUP_EN | DEVU3_WAEKUP_EN;
243 value &= ~(OTG_WAKEUP_EN | DEVU3_WAEKUP_EN);
245 cdns_imx_writel(data, USB3_INT_REG, value);
256 u32 value;
264 value = readl(xhci_regs + XECP_PM_PMCSR);
265 value &= ~PS_MASK;
266 value |= PS_D1;
267 writel(value, xhci_regs + XECP_PM_PMCSR);
270 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
271 value |= MDCTRL_CLK_SEL;
272 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
275 value = cdns_imx_readl(data, USB3_CORE_STATUS);
276 ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value,
277 (value & MDCTRL_CLK_STATUS) == MDCTRL_CLK_STATUS,
283 value = cdns_imx_readl(data, USB3_INT_REG);
284 ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value,
285 (value & LPM_CLK_REQ) != LPM_CLK_REQ,
291 value = cdns_imx_readl(data, USB3_SSPHY_STATUS);
292 ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value,
293 (value & PHY_REFCLK_REQ) != PHY_REFCLK_REQ,
303 value = readl(xhci_regs + XECP_PM_PMCSR);
304 value &= ~PS_MASK;
305 value |= PS_D0;
306 writel(value, xhci_regs + XECP_PM_PMCSR);
309 value = readl(xhci_regs + XECP_AUX_CTRL_REG1);
310 value &= ~CFG_RXDET_P3_EN;
311 writel(value, xhci_regs + XECP_AUX_CTRL_REG1);
314 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
315 value &= ~MDCTRL_CLK_SEL;
316 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
319 value = cdns_imx_readl(data, USB3_INT_REG);
320 ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value,
321 (value & CLK_125_REQ) == CLK_125_REQ,
327 value = cdns_imx_readl(data, USB3_CORE_STATUS);
328 ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value,
329 (value & MDCTRL_CLK_STATUS) != MDCTRL_CLK_STATUS,
335 value = readl(otg_regs + OTGSTS);
336 ret = readl_poll_timeout(otg_regs + OTGSTS, value,
337 (value & OTG_NRDY) != OTG_NRDY,
367 u32 value;
369 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
370 if ((value & SW_RESET_MASK) == ALL_SW_RESET)