Lines Matching refs:trb
188 struct cdns3_trb *trb)
190 u32 offset = (char *)trb - (char *)priv_ep->trb_pool;
246 * The last trb has zeroed cycle bit
302 * cdns3_ep_inc_trb - increment a trb index.
957 struct cdns3_trb *trb)
969 priv_ep->wa1_trb = trb;
996 struct cdns3_trb *trb;
1016 trb = priv_ep->trb_pool + priv_ep->enqueue;
1019 priv_req->trb = trb;
1027 trb->buffer = cpu_to_le32(TRB_BUFFER(trb_dma));
1030 trb->buffer = cpu_to_le32(TRB_BUFFER(request->sg[sg_idx].dma_address));
1036 trb->length = cpu_to_le32(TRB_BURST_LEN(16) | TRB_LEN(length));
1045 trb->length |= cpu_to_le32(TRB_TDL_SS_SIZE(tdl));
1049 trb->control = cpu_to_le32(control);
1051 trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
1054 * Memory barrier - Cycle Bit must be set before trb->length and
1055 * trb->buffer fields.
1121 struct cdns3_trb *trb;
1155 trb = priv_ep->trb_pool + priv_ep->enqueue;
1157 priv_req->trb = trb;
1195 * Fill LINK TRBs for left trb space to simply software process logic.
1198 *trb = *link_trb;
1199 trace_cdns3_prepare_trb(priv_ep, trb);
1202 trb = priv_ep->trb_pool + priv_ep->enqueue;
1203 priv_req->trb = trb;
1214 togle_pcs = cdns3_wa1_update_guard(priv_ep, trb);
1216 /* set incorrect Cycle Bit for first trb*/
1218 trb->length = 0;
1225 trb->length = cpu_to_le32(TRB_TDL_SS_SIZE(td_size));
1239 trb->buffer = cpu_to_le32(TRB_BUFFER(sg_dma_address(s)));
1242 trb->buffer = cpu_to_le32(TRB_BUFFER(trb_dma));
1275 if (ALIGN_DOWN(trb->buffer, SZ_4K) !=
1276 ALIGN_DOWN(trb->buffer + length, SZ_4K))
1279 trb->length |= cpu_to_le32(TRB_BURST_LEN(trb_burst) |
1284 * first trb should be prepared as last to avoid processing
1299 trb->control = cpu_to_le32(control);
1301 priv_req->trb->control = cpu_to_le32(control);
1304 trb->control |= cpu_to_le32(TRB_ISP);
1307 trb->control |= cpu_to_le32(TRB_CHAIN);
1316 trb = priv_ep->trb_pool + priv_ep->enqueue;
1317 trb->length = 0;
1320 trb = priv_req->trb;
1326 trb->control |= cpu_to_le32(TRB_IOC | TRB_ISP);
1346 * Memory barrier - cycle bit must be set before other filds in trb.
1352 trb->control = trb->control ^ cpu_to_le32(1);
1361 trace_cdns3_prepare_trb(priv_ep, trb + i);
1362 if (trb + i == link_trb) {
1363 trb = priv_ep->trb_pool;
1371 trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
1375 * Memory barrier - Cycle Bit must be set before trb->length and
1376 * trb->buffer fields.
1446 * cdns3_trb_handled - check whether trb has been handled by DMA
1488 struct cdns3_trb *trb;
1496 /* current trb doesn't belong to this request */
1514 trb = &priv_ep->trb_pool[priv_ep->dequeue];
1516 if ((le32_to_cpu(trb->control) & TRB_CYCLE) != priv_ep->ccs)
1552 struct cdns3_trb *trb;
1560 trb = priv_ep->trb_pool + priv_ep->dequeue;
1563 while (TRB_FIELD_TO_TYPE(le32_to_cpu(trb->control)) == TRB_LINK) {
1570 trace_cdns3_complete_trb(priv_ep, trb);
1572 trb = priv_ep->trb_pool + priv_ep->dequeue;
1586 trb = priv_ep->trb_pool + priv_ep->dequeue;
1587 trace_cdns3_complete_trb(priv_ep, trb);
1591 TRB_LEN(le32_to_cpu(trb->length));
1594 le32_to_cpu(trb->control) & TRB_SMM &&
1595 le32_to_cpu(trb->control) & TRB_CHAIN)
1622 trb = priv_ep->trb_pool;
1623 trace_cdns3_complete_trb(priv_ep, trb);
1625 if (trb != priv_req->trb)
1628 priv_req->trb, trb);
1630 request->actual += TRB_LEN(le32_to_cpu(trb->length));
2724 link_trb = priv_req->trb;
2740 if (priv_ep->wa1_trb == priv_req->trb)
2786 struct cdns3_trb *trb = NULL;
2796 trb = priv_req->trb;
2797 if (trb) {
2798 trb_tmp = *trb;
2799 trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE);
2814 if (trb)
2815 *trb = trb_tmp;