Lines Matching refs:membase
232 while ((readl(port->membase + CDNS_UART_SR) &
235 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
236 data = readl(port->membase + CDNS_UART_FIFO);
320 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
326 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
328 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO);
354 isrstatus = readl(port->membase + CDNS_UART_ISR);
355 writel(isrstatus, port->membase + CDNS_UART_ISR);
369 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
458 mreg = readl(port->membase + CDNS_UART_MR);
463 writel(mreg, port->membase + CDNS_UART_MR);
464 writel(cd, port->membase + CDNS_UART_BAUDGEN);
465 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
512 ctrl_reg = readl(port->membase + CDNS_UART_CR);
514 writel(ctrl_reg, port->membase + CDNS_UART_CR);
539 ctrl_reg = readl(port->membase + CDNS_UART_CR);
541 writel(ctrl_reg, port->membase + CDNS_UART_CR);
543 while (readl(port->membase + CDNS_UART_CR) &
552 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
553 ctrl_reg = readl(port->membase + CDNS_UART_CR);
556 writel(ctrl_reg, port->membase + CDNS_UART_CR);
582 status = readl(port->membase + CDNS_UART_CR);
585 writel(status, port->membase + CDNS_UART_CR);
590 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
595 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
606 regval = readl(port->membase + CDNS_UART_CR);
609 writel(regval, port->membase + CDNS_UART_CR);
621 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
624 regval = readl(port->membase + CDNS_UART_CR);
626 writel(regval, port->membase + CDNS_UART_CR);
639 status = readl(port->membase + CDNS_UART_SR) &
657 status = readl(port->membase + CDNS_UART_CR);
661 port->membase + CDNS_UART_CR);
665 port->membase + CDNS_UART_CR);
689 ctrl_reg = readl(port->membase + CDNS_UART_CR);
691 writel(ctrl_reg, port->membase + CDNS_UART_CR);
710 ctrl_reg = readl(port->membase + CDNS_UART_CR);
712 writel(ctrl_reg, port->membase + CDNS_UART_CR);
714 while (readl(port->membase + CDNS_UART_CR) &
722 ctrl_reg = readl(port->membase + CDNS_UART_CR);
725 writel(ctrl_reg, port->membase + CDNS_UART_CR);
727 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
747 mode_reg = readl(port->membase + CDNS_UART_MR);
788 writel(cval, port->membase + CDNS_UART_MR);
790 cval = readl(port->membase + CDNS_UART_MODEMCR);
795 writel(cval, port->membase + CDNS_UART_MODEMCR);
820 port->membase + CDNS_UART_CR);
826 port->membase + CDNS_UART_CR);
828 while (readl(port->membase + CDNS_UART_CR) &
836 status = readl(port->membase + CDNS_UART_CR);
839 writel(status, port->membase + CDNS_UART_CR);
846 port->membase + CDNS_UART_MR);
852 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
858 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
861 writel(readl(port->membase + CDNS_UART_ISR),
862 port->membase + CDNS_UART_ISR);
876 port->membase + CDNS_UART_IER);
878 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
895 status = readl(port->membase + CDNS_UART_IMR);
896 writel(status, port->membase + CDNS_UART_IDR);
897 writel(0xffffffff, port->membase + CDNS_UART_ISR);
901 port->membase + CDNS_UART_CR);
957 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
958 if (!port->membase) {
976 iounmap(port->membase);
977 port->membase = NULL;
1006 val = readl(port->membase + CDNS_UART_MODEMSR);
1028 val = readl(port->membase + CDNS_UART_MODEMCR);
1029 mode_reg = readl(port->membase + CDNS_UART_MR);
1043 writel(val, port->membase + CDNS_UART_MODEMCR);
1044 writel(mode_reg, port->membase + CDNS_UART_MR);
1056 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1059 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1073 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1077 writel(c, port->membase + CDNS_UART_FIFO);
1080 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1139 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1152 ctrl_reg = readl(port->membase + CDNS_UART_SR);
1163 writel(ch, port->membase + CDNS_UART_FIFO);
1179 if (!port->membase)
1184 port->membase + CDNS_UART_CR);
1200 writel(mr, port->membase + CDNS_UART_MR);
1201 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1202 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1240 imr = readl(port->membase + CDNS_UART_IMR);
1241 writel(imr, port->membase + CDNS_UART_IDR);
1247 ctrl = readl(port->membase + CDNS_UART_CR);
1250 writel(ctrl, port->membase + CDNS_UART_CR);
1257 writel(imr, port->membase + CDNS_UART_IER);
1280 if (!port->membase) {
1330 while (!(readl(port->membase + CDNS_UART_SR) &
1332 readl(port->membase + CDNS_UART_FIFO);
1334 writel(1, port->membase + CDNS_UART_RXWM);
1336 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1378 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1380 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1381 while (readl(port->membase + CDNS_UART_CR) &
1386 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1388 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1391 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1399 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1401 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);