Lines Matching defs:qe_port
218 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
220 if (likely((addr >= qe_port->bd_virt)) &&
221 (addr < (qe_port->bd_virt + qe_port->bd_size)))
222 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
236 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
239 if (likely((addr >= qe_port->bd_dma_addr) &&
240 (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
241 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
259 struct uart_qe_port *qe_port =
261 struct qe_bd *bdp = qe_port->tx_bd_base;
311 struct uart_qe_port *qe_port =
314 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
331 static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
336 struct uart_port *port = &qe_port->port;
342 bdp = qe_port->tx_cur;
344 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
351 bdp = qe_port->tx_bd_base;
354 qe_port->tx_cur = bdp;
367 bdp = qe_port->tx_cur;
371 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
372 while (count < qe_port->tx_fifosize) {
385 bdp = qe_port->tx_bd_base;
389 qe_port->tx_cur = bdp;
413 struct uart_qe_port *qe_port =
417 if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
421 if (qe_uart_tx_pump(qe_port))
422 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
430 struct uart_qe_port *qe_port =
433 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
444 struct uart_qe_port *qe_port =
448 ucc_slow_stop_tx(qe_port->us_private);
450 ucc_slow_restart_tx(qe_port->us_private);
457 static void qe_uart_int_rx(struct uart_qe_port *qe_port)
461 struct uart_port *port = &qe_port->port;
470 bdp = qe_port->rx_cur;
490 cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
514 bdp = qe_port->rx_bd_base;
521 qe_port->rx_cur = bdp;
565 struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
566 struct ucc_slow __iomem *uccp = qe_port->uccp;
574 uart_handle_break(&qe_port->port);
577 qe_uart_int_rx(qe_port);
580 qe_uart_tx_pump(qe_port);
589 static void qe_uart_initbd(struct uart_qe_port *qe_port)
598 bd_virt = qe_port->bd_virt;
599 bdp = qe_port->rx_bd_base;
600 qe_port->rx_cur = qe_port->rx_bd_base;
601 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
603 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
605 bd_virt += qe_port->rx_fifosize;
611 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
618 bd_virt = qe_port->bd_virt +
619 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
620 qe_port->tx_cur = qe_port->tx_bd_base;
621 bdp = qe_port->tx_bd_base;
622 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
624 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
626 bd_virt += qe_port->tx_fifosize;
632 qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
636 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
647 static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
650 struct ucc_slow __iomem *uccp = qe_port->uccp;
651 struct ucc_uart_pram *uccup = qe_port->uccup;
656 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
661 iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
755 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
759 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
770 struct uart_qe_port *qe_port =
783 qe_uart_initbd(qe_port);
784 qe_uart_init_ucc(qe_port);
788 qe_port);
795 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
796 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
806 struct uart_qe_port *qe_port =
808 struct ucc_slow __iomem *uccp = qe_port->uccp;
823 if (qe_port->wait_closing) {
826 schedule_timeout(qe_port->wait_closing);
830 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
834 ucc_slow_graceful_stop_tx(qe_port->us_private);
835 qe_uart_initbd(qe_port);
837 free_irq(port->irq, qe_port);
847 struct uart_qe_port *qe_port =
849 struct ucc_slow __iomem *uccp = qe_port->uccp;
853 struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
945 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
946 qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
948 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
949 qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
969 struct uart_qe_port *qe_port =
971 struct ucc_slow_info *us_info = &qe_port->us_info;
980 qe_port->ucc_num);
984 qe_port->us_private = uccs;
985 qe_port->uccp = uccs->us_regs;
986 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
987 qe_port->rx_bd_base = uccs->rx_bd;
988 qe_port->tx_bd_base = uccs->tx_bd;
994 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
995 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
1004 qe_port->bd_virt = bd_virt;
1005 qe_port->bd_dma_addr = bd_dma_addr;
1006 qe_port->bd_size = rx_size + tx_size;
1008 qe_port->rx_buf = bd_virt;
1009 qe_port->tx_buf = qe_port->rx_buf + rx_size;
1035 struct uart_qe_port *qe_port =
1037 struct ucc_slow_private *uccs = qe_port->us_private;
1039 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1040 qe_port->bd_dma_addr);
1244 struct uart_qe_port *qe_port = NULL;
1256 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1257 if (!qe_port) {
1273 qe_port->port.mapbase = res.start;
1290 qe_port->ucc_num = val - 1;
1306 qe_port->us_info.rx_clock = qe_clock_source(sprop);
1307 if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1308 (qe_port->us_info.rx_clock > QE_BRG16)) {
1316 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1324 qe_port->us_info.tx_clock = qe_clock_source(sprop);
1326 if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1327 (qe_port->us_info.tx_clock > QE_BRG16)) {
1339 qe_port->port.line = val;
1340 if (qe_port->port.line >= UCC_MAX_UART) {
1347 qe_port->port.irq = irq_of_parse_and_map(np, 0);
1348 if (qe_port->port.irq == 0) {
1350 qe_port->ucc_num + 1);
1377 qe_port->port.uartclk = val;
1398 qe_port->port.uartclk = val / 2;
1407 spin_lock_init(&qe_port->port.lock);
1408 qe_port->np = np;
1409 qe_port->port.dev = &ofdev->dev;
1410 qe_port->port.ops = &qe_uart_pops;
1411 qe_port->port.iotype = UPIO_MEM;
1413 qe_port->tx_nrfifos = TX_NUM_FIFO;
1414 qe_port->tx_fifosize = TX_BUF_SIZE;
1415 qe_port->rx_nrfifos = RX_NUM_FIFO;
1416 qe_port->rx_fifosize = RX_BUF_SIZE;
1418 qe_port->wait_closing = UCC_WAIT_CLOSING;
1419 qe_port->port.fifosize = 512;
1420 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1422 qe_port->us_info.ucc_num = qe_port->ucc_num;
1423 qe_port->us_info.regs = (phys_addr_t) res.start;
1424 qe_port->us_info.irq = qe_port->port.irq;
1426 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1427 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1430 qe_port->us_info.init_tx = 1;
1431 qe_port->us_info.init_rx = 1;
1437 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1440 qe_port->port.line);
1444 platform_set_drvdata(ofdev, qe_port);
1447 qe_port->ucc_num + 1, qe_port->port.line);
1451 qe_port->port.line, SERIAL_QE_MAJOR,
1452 SERIAL_QE_MINOR + qe_port->port.line);
1458 kfree(qe_port);
1464 struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
1466 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1468 uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1470 of_node_put(qe_port->np);
1472 kfree(qe_port);