Lines Matching refs:up
268 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
271 if (!ZS_REGS_HELD(up)) {
272 if (ZS_TX_ACTIVE(up)) {
273 up->flags |= SUNZILOG_FLAG_REGS_HELD;
275 __load_zsregs(channel, up->curregs);
280 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
282 unsigned int cur_cflag = up->cflag;
285 up->cflag &= ~CBAUD;
286 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
289 up->curregs[R12] = (brg & 0xff);
290 up->curregs[R13] = (brg >> 8) & 0xff;
291 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
294 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
297 if (ZS_IS_KEYB(up)) {
300 if (up->serio_open)
301 serio_interrupt(&up->serio, ch, 0);
303 } else if (ZS_IS_MOUSE(up)) {
308 sunzilog_change_mouse_baud(up);
315 if (up->serio_open)
316 serio_interrupt(&up->serio, ch, 0);
324 sunzilog_receive_chars(struct uart_sunzilog_port *up,
330 if (up->port.state != NULL) /* Unopened serial console */
331 port = &up->port.state->port;
357 ch &= up->parity_mask;
359 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
360 sunzilog_kbdms_receive_chars(up, ch, 0);
366 up->port.icount.rx++;
370 up->port.icount.brk++;
371 if (uart_handle_break(&up->port))
375 up->port.icount.parity++;
377 up->port.icount.frame++;
379 up->port.icount.overrun++;
380 r1 &= up->port.read_status_mask;
388 if (uart_handle_sysrq_char(&up->port, ch) || !port)
391 if (up->port.ignore_status_mask == 0xff ||
392 (r1 & up->port.ignore_status_mask) == 0) {
402 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
415 if (ZS_IS_MOUSE(up))
416 sunzilog_kbdms_receive_chars(up, 0, 1);
417 if (ZS_IS_CONS(up)) {
432 if (ZS_WANTS_MODEM_STATUS(up)) {
434 up->port.icount.dsr++;
440 if ((status ^ up->prev_status) ^ DCD)
441 uart_handle_dcd_change(&up->port,
443 if ((status ^ up->prev_status) ^ CTS)
444 uart_handle_cts_change(&up->port,
447 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
450 up->prev_status = status;
453 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
458 if (ZS_IS_CONS(up)) {
474 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
476 if (ZS_REGS_HELD(up)) {
477 __load_zsregs(channel, up->curregs);
478 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
481 if (ZS_TX_STOPPED(up)) {
482 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
486 if (up->port.x_char) {
487 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
488 writeb(up->port.x_char, &channel->data);
492 up->port.icount.tx++;
493 up->port.x_char = 0;
497 if (up->port.state == NULL)
499 xmit = &up->port.state->xmit;
503 if (uart_tx_stopped(&up->port))
506 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
511 uart_xmit_advance(&up->port, 1);
514 uart_write_wakeup(&up->port);
526 struct uart_sunzilog_port *up = dev_id;
528 while (up) {
530 = ZILOG_CHANNEL_FROM_PORT(&up->port);
534 spin_lock(&up->port.lock);
545 port = sunzilog_receive_chars(up, channel);
547 sunzilog_status_handle(up, channel);
549 sunzilog_transmit_chars(up, channel);
551 spin_unlock(&up->port.lock);
557 up = up->next;
558 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
560 spin_lock(&up->port.lock);
568 port = sunzilog_receive_chars(up, channel);
570 sunzilog_status_handle(up, channel);
572 sunzilog_transmit_chars(up, channel);
574 spin_unlock(&up->port.lock);
579 up = up->next;
643 struct uart_sunzilog_port *up =
660 up->curregs[R5] |= set_bits;
661 up->curregs[R5] &= ~clear_bits;
662 write_zsreg(channel, R5, up->curregs[R5]);
668 struct uart_sunzilog_port *up =
671 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
677 struct uart_sunzilog_port *up =
682 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
683 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
714 uart_write_wakeup(&up->port);
721 struct uart_sunzilog_port *up = UART_ZILOG(port);
724 if (ZS_IS_CONS(up))
730 up->curregs[R1] &= ~RxINT_MASK;
731 sunzilog_maybe_update_regs(up, channel);
737 struct uart_sunzilog_port *up =
742 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
743 if (new_reg != up->curregs[R15]) {
744 up->curregs[R15] = new_reg;
747 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
754 struct uart_sunzilog_port *up =
769 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
770 if (new_reg != up->curregs[R5]) {
771 up->curregs[R5] = new_reg;
774 write_zsreg(channel, R5, up->curregs[R5]);
780 static void __sunzilog_startup(struct uart_sunzilog_port *up)
784 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
785 up->prev_status = readb(&channel->control);
788 up->curregs[R3] |= RxENAB;
789 up->curregs[R5] |= TxENAB;
791 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
792 sunzilog_maybe_update_regs(up, channel);
797 struct uart_sunzilog_port *up = UART_ZILOG(port);
800 if (ZS_IS_CONS(up))
804 __sunzilog_startup(up);
836 struct uart_sunzilog_port *up = UART_ZILOG(port);
840 if (ZS_IS_CONS(up))
848 up->curregs[R3] &= ~RxENAB;
849 up->curregs[R5] &= ~TxENAB;
852 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
853 up->curregs[R5] &= ~SND_BRK;
854 sunzilog_maybe_update_regs(up, channel);
863 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
867 up->curregs[R10] = NRZ;
868 up->curregs[R11] = TCBR | RCBR;
871 up->curregs[R4] &= ~XCLK_MASK;
872 up->curregs[R4] |= X16CLK;
873 up->curregs[R12] = brg & 0xff;
874 up->curregs[R13] = (brg >> 8) & 0xff;
875 up->curregs[R14] = BRSRC | BRENAB;
878 up->curregs[R3] &= ~RxN_MASK;
879 up->curregs[R5] &= ~TxN_MASK;
882 up->curregs[R3] |= Rx5;
883 up->curregs[R5] |= Tx5;
884 up->parity_mask = 0x1f;
887 up->curregs[R3] |= Rx6;
888 up->curregs[R5] |= Tx6;
889 up->parity_mask = 0x3f;
892 up->curregs[R3] |= Rx7;
893 up->curregs[R5] |= Tx7;
894 up->parity_mask = 0x7f;
898 up->curregs[R3] |= Rx8;
899 up->curregs[R5] |= Tx8;
900 up->parity_mask = 0xff;
903 up->curregs[R4] &= ~0x0c;
905 up->curregs[R4] |= SB2;
907 up->curregs[R4] |= SB1;
909 up->curregs[R4] |= PAR_ENAB;
911 up->curregs[R4] &= ~PAR_ENAB;
913 up->curregs[R4] |= PAR_EVEN;
915 up->curregs[R4] &= ~PAR_EVEN;
917 up->port.read_status_mask = Rx_OVR;
919 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
921 up->port.read_status_mask |= BRK_ABRT;
923 up->port.ignore_status_mask = 0;
925 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
927 up->port.ignore_status_mask |= BRK_ABRT;
929 up->port.ignore_status_mask |= Rx_OVR;
933 up->port.ignore_status_mask = 0xff;
941 struct uart_sunzilog_port *up =
948 spin_lock_irqsave(&up->port.lock, flags);
952 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
954 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
955 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
957 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
959 up->cflag = termios->c_cflag;
961 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
965 spin_unlock_irqrestore(&up->port.lock, flags);
970 struct uart_sunzilog_port *up = UART_ZILOG(port);
972 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
1002 struct uart_sunzilog_port *up =
1005 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1030 ch &= up->parity_mask;
1037 struct uart_sunzilog_port *up =
1040 sunzilog_putchar(&up->port, ch);
1082 struct uart_sunzilog_port *up;
1093 up = &sunzilog_port_table[i];
1095 spin_lock_init(&up->port.lock);
1098 sunzilog_irq_chain = up;
1101 up->next = up + 1;
1103 up->next = NULL;
1154 struct uart_sunzilog_port *up = serio->port_data;
1159 sunzilog_putchar(&up->port, ch);
1168 struct uart_sunzilog_port *up = serio->port_data;
1173 if (!up->serio_open) {
1174 up->serio_open = 1;
1185 struct uart_sunzilog_port *up = serio->port_data;
1189 up->serio_open = 0;
1199 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1203 if (up->port.sysrq || oops_in_progress)
1204 locked = spin_trylock_irqsave(&up->port.lock, flags);
1206 spin_lock_irqsave(&up->port.lock, flags);
1208 uart_console_write(&up->port, s, count, sunzilog_putchar);
1212 spin_unlock_irqrestore(&up->port.lock, flags);
1217 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1221 if (up->port.type != PORT_SUNZILOG)
1228 sunserial_console_termios(con, up->port.dev->of_node);
1247 spin_lock_irqsave(&up->port.lock, flags);
1249 up->curregs[R15] |= BRKIE;
1250 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1252 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1253 __sunzilog_startup(up);
1255 spin_unlock_irqrestore(&up->port.lock, flags);
1279 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1283 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1284 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1287 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1291 up->curregs[R15] |= BRKIE;
1293 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1294 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1295 __sunzilog_startup(up);
1299 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1301 struct serio *serio = &up->serio;
1303 serio->port_data = up;
1306 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1315 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1322 serio->dev.parent = up->port.dev;
1328 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1334 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1336 spin_lock_irqsave(&up->port.lock, flags);
1337 if (ZS_IS_CHANNEL_A(up)) {
1343 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1345 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1346 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1347 up->curregs[R3] = RxENAB | Rx8;
1348 up->curregs[R5] = TxENAB | Tx8;
1349 up->curregs[R6] = 0x00; /* SDLC Address */
1350 up->curregs[R7] = 0x7E; /* SDLC Flag */
1351 up->curregs[R9] = NV;
1352 up->curregs[R7p] = 0x00;
1353 sunzilog_init_kbdms(up);
1355 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1356 up->curregs[R9] |= MIE;
1357 write_zsreg(channel, R9, up->curregs[R9]);
1360 up->parity_mask = 0xff;
1361 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1362 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1363 up->curregs[R3] = RxENAB | Rx8;
1364 up->curregs[R5] = TxENAB | Tx8;
1365 up->curregs[R6] = 0x00; /* SDLC Address */
1366 up->curregs[R7] = 0x7E; /* SDLC Flag */
1367 up->curregs[R9] = NV;
1368 up->curregs[R10] = NRZ;
1369 up->curregs[R11] = TCBR | RCBR;
1372 up->curregs[R12] = (brg & 0xff);
1373 up->curregs[R13] = (brg >> 8) & 0xff;
1374 up->curregs[R14] = BRSRC | BRENAB;
1375 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1376 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1377 if (__load_zsregs(channel, up->curregs)) {
1378 up->flags |= SUNZILOG_FLAG_ESCC;
1381 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1382 up->curregs[R9] |= MIE;
1383 write_zsreg(channel, R9, up->curregs[R9]);
1386 spin_unlock_irqrestore(&up->port.lock, flags);
1389 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1391 sunzilog_register_serio(up);
1401 struct uart_sunzilog_port *up;
1426 up = &sunzilog_port_table[inst * 2];
1429 up[0].port.mapbase = op->resource[0].start + 0x00;
1430 up[0].port.membase = (void __iomem *) &rp->channelA;
1431 up[0].port.iotype = UPIO_MEM;
1432 up[0].port.irq = op->archdata.irqs[0];
1433 up[0].port.uartclk = ZS_CLOCK;
1434 up[0].port.fifosize = 1;
1435 up[0].port.ops = &sunzilog_pops;
1436 up[0].port.type = PORT_SUNZILOG;
1437 up[0].port.flags = 0;
1438 up[0].port.line = (inst * 2) + 0;
1439 up[0].port.dev = &op->dev;
1440 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1441 up[0].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1443 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1444 sunzilog_init_hw(&up[0]);
1447 up[1].port.mapbase = op->resource[0].start + 0x04;
1448 up[1].port.membase = (void __iomem *) &rp->channelB;
1449 up[1].port.iotype = UPIO_MEM;
1450 up[1].port.irq = op->archdata.irqs[0];
1451 up[1].port.uartclk = ZS_CLOCK;
1452 up[1].port.fifosize = 1;
1453 up[1].port.ops = &sunzilog_pops;
1454 up[1].port.type = PORT_SUNZILOG;
1455 up[1].port.flags = 0;
1456 up[1].port.line = (inst * 2) + 1;
1457 up[1].port.dev = &op->dev;
1458 up[1].flags |= 0;
1459 up[1].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1461 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1462 sunzilog_init_hw(&up[1]);
1466 &sunzilog_reg, up[0].port.line,
1468 up->flags |= SUNZILOG_FLAG_IS_CONS;
1469 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1476 &sunzilog_reg, up[1].port.line,
1478 up->flags |= SUNZILOG_FLAG_IS_CONS;
1479 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1481 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1491 (unsigned long long) up[0].port.mapbase,
1492 op->archdata.irqs[0], sunzilog_type(&up[0].port));
1496 (unsigned long long) up[1].port.mapbase,
1497 op->archdata.irqs[0], sunzilog_type(&up[1].port));
1501 platform_set_drvdata(op, &up[0]);
1506 static void zs_remove_one(struct uart_sunzilog_port *up)
1508 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1510 serio_unregister_port(&up->serio);
1513 uart_remove_one_port(&sunzilog_reg, &up->port);
1518 struct uart_sunzilog_port *up = platform_get_drvdata(op);
1521 zs_remove_one(&up[0]);
1522 zs_remove_one(&up[1]);
1524 regs = sunzilog_chip_regs[up[0].port.line / 2];
1578 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1585 while (up) {
1588 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1589 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1590 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
1591 up->curregs[R9] |= MIE;
1592 write_zsreg(channel, R9, up->curregs[R9]);
1593 up = up->next;
1619 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1622 while (up) {
1625 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1626 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1627 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
1628 up->curregs[R9] &= ~MIE;
1629 write_zsreg(channel, R9, up->curregs[R9]);
1630 up = up->next;