Lines Matching refs:curregs
77 unsigned char curregs[NUM_ZSREGS];
275 __load_zsregs(channel, up->curregs);
289 up->curregs[R12] = (brg & 0xff);
290 up->curregs[R13] = (brg >> 8) & 0xff;
477 __load_zsregs(channel, up->curregs);
660 up->curregs[R5] |= set_bits;
661 up->curregs[R5] &= ~clear_bits;
662 write_zsreg(channel, R5, up->curregs[R5]);
730 up->curregs[R1] &= ~RxINT_MASK;
742 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
743 if (new_reg != up->curregs[R15]) {
744 up->curregs[R15] = new_reg;
747 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
769 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
770 if (new_reg != up->curregs[R5]) {
771 up->curregs[R5] = new_reg;
774 write_zsreg(channel, R5, up->curregs[R5]);
788 up->curregs[R3] |= RxENAB;
789 up->curregs[R5] |= TxENAB;
791 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
848 up->curregs[R3] &= ~RxENAB;
849 up->curregs[R5] &= ~TxENAB;
852 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
853 up->curregs[R5] &= ~SND_BRK;
867 up->curregs[R10] = NRZ;
868 up->curregs[R11] = TCBR | RCBR;
871 up->curregs[R4] &= ~XCLK_MASK;
872 up->curregs[R4] |= X16CLK;
873 up->curregs[R12] = brg & 0xff;
874 up->curregs[R13] = (brg >> 8) & 0xff;
875 up->curregs[R14] = BRSRC | BRENAB;
878 up->curregs[R3] &= ~RxN_MASK;
879 up->curregs[R5] &= ~TxN_MASK;
882 up->curregs[R3] |= Rx5;
883 up->curregs[R5] |= Tx5;
887 up->curregs[R3] |= Rx6;
888 up->curregs[R5] |= Tx6;
892 up->curregs[R3] |= Rx7;
893 up->curregs[R5] |= Tx7;
898 up->curregs[R3] |= Rx8;
899 up->curregs[R5] |= Tx8;
903 up->curregs[R4] &= ~0x0c;
905 up->curregs[R4] |= SB2;
907 up->curregs[R4] |= SB1;
909 up->curregs[R4] |= PAR_ENAB;
911 up->curregs[R4] &= ~PAR_ENAB;
913 up->curregs[R4] |= PAR_EVEN;
915 up->curregs[R4] &= ~PAR_EVEN;
1249 up->curregs[R15] |= BRKIE;
1291 up->curregs[R15] |= BRKIE;
1345 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1346 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1347 up->curregs[R3] = RxENAB | Rx8;
1348 up->curregs[R5] = TxENAB | Tx8;
1349 up->curregs[R6] = 0x00; /* SDLC Address */
1350 up->curregs[R7] = 0x7E; /* SDLC Flag */
1351 up->curregs[R9] = NV;
1352 up->curregs[R7p] = 0x00;
1356 up->curregs[R9] |= MIE;
1357 write_zsreg(channel, R9, up->curregs[R9]);
1361 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1362 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1363 up->curregs[R3] = RxENAB | Rx8;
1364 up->curregs[R5] = TxENAB | Tx8;
1365 up->curregs[R6] = 0x00; /* SDLC Address */
1366 up->curregs[R7] = 0x7E; /* SDLC Flag */
1367 up->curregs[R9] = NV;
1368 up->curregs[R10] = NRZ;
1369 up->curregs[R11] = TCBR | RCBR;
1372 up->curregs[R12] = (brg & 0xff);
1373 up->curregs[R13] = (brg >> 8) & 0xff;
1374 up->curregs[R14] = BRSRC | BRENAB;
1375 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1376 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1377 if (__load_zsregs(channel, up->curregs)) {
1382 up->curregs[R9] |= MIE;
1383 write_zsreg(channel, R9, up->curregs[R9]);
1591 up->curregs[R9] |= MIE;
1592 write_zsreg(channel, R9, up->curregs[R9]);
1628 up->curregs[R9] &= ~MIE;
1629 write_zsreg(channel, R9, up->curregs[R9]);