Lines Matching refs:up
92 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
94 int timeout = up->tec_timeout;
96 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
100 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
102 int timeout = up->cec_timeout;
104 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
109 receive_chars(struct uart_sunsab_port *up,
119 if (up->port.state != NULL) /* Unopened serial console */
120 port = &up->port.state->port;
129 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
135 sunsab_cec_wait(up);
136 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
145 buf[i] = readb(&up->regs->r.rfifo[i]);
149 sunsab_cec_wait(up);
150 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
155 (up->port.line == up->port.cons->index))
162 up->port.icount.brk++;
163 uart_handle_break(&up->port);
171 up->port.icount.rx++;
183 up->port.icount.brk++;
190 if (uart_handle_break(&up->port))
193 up->port.icount.parity++;
195 up->port.icount.frame++;
197 up->port.icount.overrun++;
202 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
203 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
213 if (uart_handle_sysrq_char(&up->port, ch) || !port)
216 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
217 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
232 static void transmit_chars(struct uart_sunsab_port *up,
235 struct circ_buf *xmit = &up->port.state->xmit;
239 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
240 writeb(up->interrupt_mask1, &up->regs->w.imr1);
241 set_bit(SAB82532_ALLS, &up->irqflags);
249 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
252 set_bit(SAB82532_XPR, &up->irqflags);
253 sunsab_tx_idle(up);
255 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
256 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
257 writeb(up->interrupt_mask1, &up->regs->w.imr1);
261 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
262 writeb(up->interrupt_mask1, &up->regs->w.imr1);
263 clear_bit(SAB82532_ALLS, &up->irqflags);
266 clear_bit(SAB82532_XPR, &up->irqflags);
267 for (i = 0; i < up->port.fifosize; i++) {
269 &up->regs->w.xfifo[i]);
270 uart_xmit_advance(&up->port, 1);
276 sunsab_cec_wait(up);
277 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
280 uart_write_wakeup(&up->port);
283 sunsab_stop_tx(&up->port);
286 static void check_status(struct uart_sunsab_port *up,
290 uart_handle_dcd_change(&up->port,
291 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
294 uart_handle_cts_change(&up->port,
295 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
297 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
298 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
299 up->port.icount.dsr++;
302 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
307 struct uart_sunsab_port *up = dev_id;
313 spin_lock_irqsave(&up->port.lock, flags);
316 gis = readb(&up->regs->r.gis) >> up->gis_shift;
318 status.sreg.isr0 = readb(&up->regs->r.isr0);
320 status.sreg.isr1 = readb(&up->regs->r.isr1);
326 port = receive_chars(up, &status);
329 check_status(up, &status);
331 transmit_chars(up, &status);
334 spin_unlock_irqrestore(&up->port.lock, flags);
345 struct uart_sunsab_port *up =
350 if (test_bit(SAB82532_ALLS, &up->irqflags))
361 struct uart_sunsab_port *up =
365 up->cached_mode &= ~SAB82532_MODE_FRTS;
366 up->cached_mode |= SAB82532_MODE_RTS;
368 up->cached_mode |= (SAB82532_MODE_FRTS |
372 up->cached_pvr &= ~(up->pvr_dtr_bit);
374 up->cached_pvr |= up->pvr_dtr_bit;
377 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
378 if (test_bit(SAB82532_XPR, &up->irqflags))
379 sunsab_tx_idle(up);
385 struct uart_sunsab_port *up =
392 val = readb(&up->regs->r.pvr);
393 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
395 val = readb(&up->regs->r.vstr);
398 val = readb(&up->regs->r.star);
407 struct uart_sunsab_port *up =
410 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
411 writeb(up->interrupt_mask1, &up->regs->w.imr1);
415 static void sunsab_tx_idle(struct uart_sunsab_port *up)
417 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
420 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
421 writeb(up->cached_mode, &up->regs->rw.mode);
422 writeb(up->cached_pvr, &up->regs->rw.pvr);
423 writeb(up->cached_dafo, &up->regs->w.dafo);
425 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
426 tmp = readb(&up->regs->rw.ccr2);
428 tmp |= (up->cached_ebrg >> 2) & 0xc0;
429 writeb(tmp, &up->regs->rw.ccr2);
436 struct uart_sunsab_port *up =
438 struct circ_buf *xmit = &up->port.state->xmit;
444 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
445 writeb(up->interrupt_mask1, &up->regs->w.imr1);
447 if (!test_bit(SAB82532_XPR, &up->irqflags))
450 clear_bit(SAB82532_ALLS, &up->irqflags);
451 clear_bit(SAB82532_XPR, &up->irqflags);
453 for (i = 0; i < up->port.fifosize; i++) {
455 &up->regs->w.xfifo[i]);
456 uart_xmit_advance(&up->port, 1);
462 sunsab_cec_wait(up);
463 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
469 struct uart_sunsab_port *up =
476 spin_lock_irqsave(&up->port.lock, flags);
478 sunsab_tec_wait(up);
479 writeb(ch, &up->regs->w.tic);
481 spin_unlock_irqrestore(&up->port.lock, flags);
487 struct uart_sunsab_port *up =
490 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
491 writeb(up->interrupt_mask1, &up->regs->w.imr0);
497 struct uart_sunsab_port *up =
502 spin_lock_irqsave(&up->port.lock, flags);
504 val = up->cached_dafo;
509 up->cached_dafo = val;
511 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
512 if (test_bit(SAB82532_XPR, &up->irqflags))
513 sunsab_tx_idle(up);
515 spin_unlock_irqrestore(&up->port.lock, flags);
521 struct uart_sunsab_port *up =
525 int err = request_irq(up->port.irq, sunsab_interrupt,
526 IRQF_SHARED, "sab", up);
530 spin_lock_irqsave(&up->port.lock, flags);
535 sunsab_cec_wait(up);
536 sunsab_tec_wait(up);
541 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
542 sunsab_cec_wait(up);
543 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
548 (void) readb(&up->regs->r.isr0);
549 (void) readb(&up->regs->r.isr1);
554 writeb(0, &up->regs->w.ccr0); /* power-down */
556 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
557 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
559 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
560 writeb(0, &up->regs->w.ccr3);
561 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
562 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
564 writeb(up->cached_mode, &up->regs->w.mode);
565 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
567 tmp = readb(&up->regs->rw.ccr0);
568 tmp |= SAB82532_CCR0_PU; /* power-up */
569 writeb(tmp, &up->regs->rw.ccr0);
574 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
576 writeb(up->interrupt_mask0, &up->regs->w.imr0);
577 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
581 writeb(up->interrupt_mask1, &up->regs->w.imr1);
582 set_bit(SAB82532_ALLS, &up->irqflags);
583 set_bit(SAB82532_XPR, &up->irqflags);
585 spin_unlock_irqrestore(&up->port.lock, flags);
593 struct uart_sunsab_port *up =
597 spin_lock_irqsave(&up->port.lock, flags);
600 up->interrupt_mask0 = 0xff;
601 writeb(up->interrupt_mask0, &up->regs->w.imr0);
602 up->interrupt_mask1 = 0xff;
603 writeb(up->interrupt_mask1, &up->regs->w.imr1);
606 up->cached_dafo = readb(&up->regs->rw.dafo);
607 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
608 writeb(up->cached_dafo, &up->regs->rw.dafo);
611 up->cached_mode &= ~SAB82532_MODE_RAC;
612 writeb(up->cached_mode, &up->regs->rw.mode);
626 tmp = readb(&up->regs->rw.ccr0);
628 writeb(tmp, &up->regs->rw.ccr0);
631 spin_unlock_irqrestore(&up->port.lock, flags);
632 free_irq(up->port.irq, up);
678 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
706 up->cached_dafo = dafo;
710 up->cached_ebrg = n | (m << 6);
712 up->tec_timeout = (10 * 1000000) / baud;
713 up->cec_timeout = up->tec_timeout >> 2;
724 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
727 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
731 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
734 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
739 up->port.ignore_status_mask = 0;
741 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
744 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
750 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
757 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
760 uart_update_timeout(&up->port, cflag,
761 (up->port.uartclk / (16 * quot)));
766 up->cached_mode |= SAB82532_MODE_RAC;
767 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
768 if (test_bit(SAB82532_XPR, &up->irqflags))
769 sunsab_tx_idle(up);
776 struct uart_sunsab_port *up =
782 spin_lock_irqsave(&up->port.lock, flags);
783 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
784 spin_unlock_irqrestore(&up->port.lock, flags);
789 struct uart_sunsab_port *up = (void *)port;
792 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
846 struct uart_sunsab_port *up =
849 sunsab_tec_wait(up);
850 writeb(c, &up->regs->w.tic);
855 struct uart_sunsab_port *up = &sunsab_ports[con->index];
859 if (up->port.sysrq || oops_in_progress)
860 locked = spin_trylock_irqsave(&up->port.lock, flags);
862 spin_lock_irqsave(&up->port.lock, flags);
864 uart_console_write(&up->port, s, n, sunsab_console_putchar);
865 sunsab_tec_wait(up);
868 spin_unlock_irqrestore(&up->port.lock, flags);
873 struct uart_sunsab_port *up = &sunsab_ports[con->index];
883 if (up->port.type != PORT_SUNSAB)
889 sunserial_console_termios(con, up->port.dev->of_node);
910 spin_lock_init(&up->port.lock);
915 sunsab_startup(&up->port);
917 spin_lock_irqsave(&up->port.lock, flags);
922 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
924 writeb(up->interrupt_mask0, &up->regs->w.imr0);
925 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
929 writeb(up->interrupt_mask1, &up->regs->w.imr1);
931 quot = uart_get_divisor(&up->port, baud);
932 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
933 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
935 spin_unlock_irqrestore(&up->port.lock, flags);
959 static int sunsab_init_one(struct uart_sunsab_port *up,
964 up->port.line = line;
965 up->port.dev = &op->dev;
967 up->port.mapbase = op->resource[0].start + offset;
968 up->port.membase = of_ioremap(&op->resource[0], offset,
971 if (!up->port.membase)
973 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
975 up->port.irq = op->archdata.irqs[0];
977 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
978 up->port.iotype = UPIO_MEM;
979 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE);
981 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
983 up->port.ops = &sunsab_pops;
984 up->port.type = PORT_SUNSAB;
985 up->port.uartclk = SAB_BASE_BAUD;
987 up->type = readb(&up->regs->r.vstr) & 0x0f;
988 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
989 writeb(0xff, &up->regs->w.pim);
990 if ((up->port.line & 0x1) == 0) {
991 up->pvr_dsr_bit = (1 << 0);
992 up->pvr_dtr_bit = (1 << 1);
993 up->gis_shift = 2;
995 up->pvr_dsr_bit = (1 << 3);
996 up->pvr_dtr_bit = (1 << 2);
997 up->gis_shift = 0;
999 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1000 writeb(up->cached_pvr, &up->regs->w.pvr);
1001 up->cached_mode = readb(&up->regs->rw.mode);
1002 up->cached_mode |= SAB82532_MODE_FRTS;
1003 writeb(up->cached_mode, &up->regs->rw.mode);
1004 up->cached_mode |= SAB82532_MODE_RTS;
1005 writeb(up->cached_mode, &up->regs->rw.mode);
1007 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1008 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1016 struct uart_sunsab_port *up;
1019 up = &sunsab_ports[inst * 2];
1021 err = sunsab_init_one(&up[0], op,
1027 err = sunsab_init_one(&up[1], op,
1034 &sunsab_reg, up[0].port.line,
1038 &sunsab_reg, up[1].port.line,
1041 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1045 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1049 platform_set_drvdata(op, &up[0]);
1056 uart_remove_one_port(&sunsab_reg, &up[0].port);
1059 up[1].port.membase,
1063 up[0].port.membase,
1071 struct uart_sunsab_port *up = platform_get_drvdata(op);
1073 uart_remove_one_port(&sunsab_reg, &up[1].port);
1074 uart_remove_one_port(&sunsab_reg, &up[0].port);
1076 up[1].port.membase,
1079 up[0].port.membase,