Lines Matching refs:cr1
46 .cr1 = 0x0c,
63 .cr1 = 0x00,
85 .cr1 = 0x00,
181 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
189 over8 = *cr1 & USART_CR1_OVER8;
191 *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
203 *cr1 |= rs485_deat_dedt;
215 *cr1 |= rs485_deat_dedt;
224 u32 usartdiv, baud, cr1, cr3;
227 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
230 cr1 = readl_relaxed(port->membase + ofs->cr1);
234 over8 = cr1 & USART_CR1_OVER8;
241 stm32_usart_config_reg_rs485(&cr1, &cr3,
252 writel_relaxed(cr1, port->membase + ofs->cr1);
260 stm32_usart_clr_bits(port, ofs->cr1,
264 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
661 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
669 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
680 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
688 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);
1002 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1018 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
1043 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1087 stm32_usart_set_bits(port, ofs->cr1, val);
1134 stm32_usart_clr_bits(port, ofs->cr1, val);
1150 u32 cr1, cr2, cr3, isr;
1171 writel_relaxed(0, port->membase + ofs->cr1);
1178 cr1 = USART_CR1_TE | USART_CR1_RE;
1180 cr1 |= USART_CR1_FIFOEN;
1201 cr1 |= USART_CR1_PCE;
1209 * M0 and M1 already cleared by cr1 initialization.
1212 cr1 |= USART_CR1_M0;
1214 cr1 |= USART_CR1_M1;
1224 cr1 |= USART_CR1_M0;
1247 cr1 |= stm32_port->cr1_irq;
1251 cr1 |= USART_CR1_PS;
1269 cr1 |= USART_CR1_OVER8;
1270 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
1273 cr1 &= ~USART_CR1_OVER8;
1274 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
1312 cr1 |= USART_CR1_PEIE;
1322 stm32_usart_config_reg_rs485(&cr1, &cr3,
1336 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
1347 writel_relaxed(cr1, port->membase + ofs->cr1);
1349 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1401 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1826 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);
1890 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1893 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1898 writel_relaxed(old_cr1, port->membase + ofs->cr1);
2026 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
2055 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);