Lines Matching defs:stm32_port
111 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
113 return container_of(port, struct stm32_port, port);
136 struct stm32_port *stm32_port = to_stm32_port(port);
137 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
147 struct stm32_port *stm32_port = to_stm32_port(port);
150 if (stm32_port->hw_flow_control ||
155 mctrl_gpio_set(stm32_port->gpios,
156 stm32_port->port.mctrl | TIOCM_RTS);
158 mctrl_gpio_set(stm32_port->gpios,
159 stm32_port->port.mctrl & ~TIOCM_RTS);
165 struct stm32_port *stm32_port = to_stm32_port(port);
168 if (stm32_port->hw_flow_control ||
173 mctrl_gpio_set(stm32_port->gpios,
174 stm32_port->port.mctrl & ~TIOCM_RTS);
176 mctrl_gpio_set(stm32_port->gpios,
177 stm32_port->port.mctrl | TIOCM_RTS);
221 struct stm32_port *stm32_port = to_stm32_port(port);
222 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
223 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
290 static bool stm32_usart_rx_dma_started(struct stm32_port *stm32_port)
292 return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false;
295 static void stm32_usart_rx_dma_terminate(struct stm32_port *stm32_port)
297 dmaengine_terminate_async(stm32_port->rx_ch);
298 stm32_port->rx_dma_busy = false;
301 static int stm32_usart_dma_pause_resume(struct stm32_port *stm32_port,
305 bool stm32_usart_xx_dma_started(struct stm32_port *),
306 void stm32_usart_xx_dma_terminate(struct stm32_port *))
308 struct uart_port *port = &stm32_port->port;
312 if (!stm32_usart_xx_dma_started(stm32_port))
322 stm32_usart_xx_dma_terminate(stm32_port);
327 static int stm32_usart_rx_dma_pause(struct stm32_port *stm32_port)
329 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
335 static int stm32_usart_rx_dma_resume(struct stm32_port *stm32_port)
337 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
346 struct stm32_port *stm32_port = to_stm32_port(port);
347 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
353 if (!stm32_usart_rx_dma_started(stm32_port))
366 struct stm32_port *stm32_port = to_stm32_port(port);
367 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
372 c &= stm32_port->rdr_mask;
379 struct stm32_port *stm32_port = to_stm32_port(port);
380 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
445 struct stm32_port *stm32_port = to_stm32_port(port);
446 struct tty_port *ttyport = &stm32_port->port.state->port;
450 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res);
457 if (!(stm32_port->rdr_mask == (BIT(8) - 1)))
459 *(dma_start + i) &= stm32_port->rdr_mask;
465 stm32_port->last_res -= dma_count;
466 if (stm32_port->last_res == 0)
467 stm32_port->last_res = RX_BUF_L;
472 struct stm32_port *stm32_port = to_stm32_port(port);
476 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) {
478 dma_size = stm32_port->last_res;
483 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue;
492 struct stm32_port *stm32_port = to_stm32_port(port);
493 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
498 if (stm32_usart_rx_dma_started(stm32_port) || force_dma_flush) {
499 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
500 stm32_port->rx_ch->cookie,
501 &stm32_port->rx_dma_state);
519 stm32_usart_rx_dma_terminate(stm32_port);
547 struct stm32_port *stm32_port = to_stm32_port(port);
552 if (stm32_port->throttled)
555 if (stm32_port->rx_dma_busy) {
556 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
557 stm32_port->rx_ch->cookie,
562 if (rx_dma_status == DMA_PAUSED && !stm32_usart_rx_dma_resume(stm32_port))
566 stm32_usart_rx_dma_terminate(stm32_port);
569 stm32_port->rx_dma_busy = true;
571 stm32_port->last_res = RX_BUF_L;
573 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
574 stm32_port->rx_dma_buf,
580 stm32_port->rx_dma_busy = false;
590 dmaengine_terminate_sync(stm32_port->rx_ch);
591 stm32_port->rx_dma_busy = false;
596 dma_async_issue_pending(stm32_port->rx_ch);
601 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
603 dmaengine_terminate_async(stm32_port->tx_ch);
604 stm32_port->tx_dma_busy = false;
607 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
616 return stm32_port->tx_dma_busy;
619 static int stm32_usart_tx_dma_pause(struct stm32_port *stm32_port)
621 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
627 static int stm32_usart_tx_dma_resume(struct stm32_port *stm32_port)
629 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
638 struct stm32_port *stm32port = to_stm32_port(port);
651 struct stm32_port *stm32_port = to_stm32_port(port);
652 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
658 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
666 struct stm32_port *stm32_port = to_stm32_port(port);
667 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
674 struct stm32_port *stm32_port = to_stm32_port(port);
675 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
677 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
685 struct stm32_port *stm32_port = to_stm32_port(port);
686 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
693 struct stm32_port *stm32_port = to_stm32_port(port);
694 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
714 struct stm32_port *stm32port = to_stm32_port(port);
789 struct stm32_port *stm32_port = to_stm32_port(port);
790 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
795 if (!stm32_port->hw_flow_control &&
805 stm32_usart_tx_dma_pause(stm32_port);
821 stm32_usart_tx_dma_resume(stm32_port);
835 if (stm32_port->tx_ch)
845 if (!stm32_port->hw_flow_control &&
856 struct stm32_port *stm32_port = to_stm32_port(port);
857 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
863 if (!stm32_port->hw_flow_control &&
887 if (!stm32_port->throttled) {
888 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) ||
889 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) {
898 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
905 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) {
918 struct stm32_port *stm32_port = to_stm32_port(port);
919 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
926 mctrl_gpio_set(stm32_port->gpios, mctrl);
931 struct stm32_port *stm32_port = to_stm32_port(port);
937 return mctrl_gpio_get(stm32_port->gpios, &ret);
953 struct stm32_port *stm32_port = to_stm32_port(port);
958 stm32_usart_tx_dma_pause(stm32_port);
981 struct stm32_port *stm32_port = to_stm32_port(port);
983 if (stm32_port->tx_ch)
984 stm32_usart_tx_dma_terminate(stm32_port);
990 struct stm32_port *stm32_port = to_stm32_port(port);
991 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1000 stm32_usart_rx_dma_pause(stm32_port);
1002 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1003 if (stm32_port->cr3_irq)
1004 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1006 stm32_port->throttled = true;
1013 struct stm32_port *stm32_port = to_stm32_port(port);
1014 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1018 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
1019 if (stm32_port->cr3_irq)
1020 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
1022 stm32_port->throttled = false;
1028 if (stm32_port->rx_ch)
1037 struct stm32_port *stm32_port = to_stm32_port(port);
1038 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1041 stm32_usart_rx_dma_pause(stm32_port);
1043 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1044 if (stm32_port->cr3_irq)
1045 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1055 struct stm32_port *stm32_port = to_stm32_port(port);
1056 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1057 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1067 if (stm32_port->swap) {
1077 if (stm32_port->rx_ch) {
1086 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
1094 struct stm32_port *stm32_port = to_stm32_port(port);
1095 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1096 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1100 if (stm32_usart_tx_dma_started(stm32_port))
1101 stm32_usart_tx_dma_terminate(stm32_port);
1103 if (stm32_port->tx_ch)
1110 val |= stm32_port->cr1_irq | USART_CR1_RE;
1112 if (stm32_port->fifoen)
1124 if (stm32_port->rx_ch) {
1125 stm32_usart_rx_dma_terminate(stm32_port);
1126 dmaengine_synchronize(stm32_port->rx_ch);
1143 struct stm32_port *stm32_port = to_stm32_port(port);
1144 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1145 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1154 if (!stm32_port->hw_flow_control)
1179 if (stm32_port->fifoen)
1181 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
1186 if (stm32_port->fifoen) {
1187 if (stm32_port->txftcfg >= 0)
1188 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
1189 if (stm32_port->rxftcfg >= 0)
1190 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
1197 stm32_port->rdr_mask = (BIT(bits) - 1);
1228 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
1229 (stm32_port->fifoen &&
1230 stm32_port->rxftcfg >= 0))) {
1237 stm32_port->cr1_irq = USART_CR1_RTOIE;
1244 stm32_port->cr3_irq = USART_CR3_RXFTIE;
1247 cr1 |= stm32_port->cr1_irq;
1248 cr3 |= stm32_port->cr3_irq;
1307 if (stm32_port->rx_ch) {
1318 if (stm32_port->tx_ch)
1340 if (stm32_port->wakeup_src) {
1389 struct stm32_port *stm32port = container_of(port,
1390 struct stm32_port, port);
1413 struct stm32_port *stm32_port = to_stm32_port(port);
1415 return clk_prepare_enable(stm32_port->clk);
1420 struct stm32_port *stm32_port = to_stm32_port(port);
1421 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1426 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
1496 static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1508 static int stm32_usart_init_port(struct stm32_port *stm32port,
1596 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1634 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1642 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1672 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1680 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1712 struct stm32_port *stm32port;
1815 struct stm32_port *stm32_port = to_stm32_port(port);
1816 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1828 if (stm32_port->tx_ch) {
1829 stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1830 dma_release_channel(stm32_port->tx_ch);
1833 if (stm32_port->rx_ch) {
1834 stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1835 dma_release_channel(stm32_port->rx_ch);
1845 if (stm32_port->wakeup_src) {
1850 stm32_usart_deinit_port(stm32_port);
1857 struct stm32_port *stm32_port = to_stm32_port(port);
1858 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1877 struct stm32_port *stm32_port = to_stm32_port(port);
1878 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1879 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1906 struct stm32_port *stm32port;
2011 struct stm32_port *stm32_port = to_stm32_port(port);
2012 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
2018 if (!stm32_port->wakeup_src || !tty_port_initialized(tport))
2028 mctrl_gpio_enable_irq_wake(stm32_port->gpios);
2035 if (stm32_port->rx_ch) {
2038 if (!stm32_usart_rx_dma_pause(stm32_port))
2040 stm32_usart_rx_dma_terminate(stm32_port);
2049 if (stm32_port->rx_ch) {
2054 mctrl_gpio_disable_irq_wake(stm32_port->gpios);
2110 struct stm32_port *stm32port = container_of(port,
2111 struct stm32_port, port);
2121 struct stm32_port *stm32port = container_of(port,
2122 struct stm32_port, port);