Lines Matching refs:ssp
218 * @ssp: pointer to a struct sifive_serial_port record
221 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
225 static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
227 __ssp_early_writel(v, offs, &ssp->port);
232 * @ssp: pointer to a struct sifive_serial_port record
236 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
242 static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs)
244 return __ssp_early_readl(&ssp->port, offs);
249 * @ssp: pointer to a struct sifive_serial_port
258 static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp)
260 return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) &
266 * @ssp: pointer to a struct sifive_serial_port
269 * Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the
275 static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch)
277 __ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp);
282 * @ssp: pointer to a struct sifive_serial_port
287 * Context: Any context. Expects @ssp->port.lock to be held by caller.
289 static void __ssp_transmit_chars(struct sifive_serial_port *ssp)
293 uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH,
295 __ssp_transmit_char(ssp, ch),
301 * @ssp: pointer to a struct sifive_serial_port
304 * on the SiFive UART referred to by @ssp.
306 static void __ssp_enable_txwm(struct sifive_serial_port *ssp)
308 if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)
311 ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;
312 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
317 * @ssp: pointer to a struct sifive_serial_port
320 * on the SiFive UART referred to by @ssp.
322 static void __ssp_enable_rxwm(struct sifive_serial_port *ssp)
324 if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)
327 ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;
328 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
333 * @ssp: pointer to a struct sifive_serial_port
336 * on the UART referred to by @ssp.
338 static void __ssp_disable_txwm(struct sifive_serial_port *ssp)
340 if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))
343 ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;
344 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
349 * @ssp: pointer to a struct sifive_serial_port
352 * on the UART referred to by @ssp.
354 static void __ssp_disable_rxwm(struct sifive_serial_port *ssp)
356 if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))
359 ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;
360 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
365 * @ssp: pointer to a struct sifive_serial_port
369 * @ssp, and to return it. Also returns the RX FIFO empty bit in
375 static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty)
380 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
396 * @ssp: pointer to a struct sifive_serial_port
399 * to by @ssp and pass them up to the Linux serial layer.
401 * Context: Expects ssp->port.lock to be held by caller.
403 static void __ssp_receive_chars(struct sifive_serial_port *ssp)
410 ch = __ssp_receive_char(ssp, &is_empty);
414 ssp->port.icount.rx++;
415 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);
418 tty_flip_buffer_push(&ssp->port.state->port);
423 * @ssp: pointer to a struct sifive_serial_port
426 * and target line rate referred to by @ssp and write it into the
429 static void __ssp_update_div(struct sifive_serial_port *ssp)
433 div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;
435 __ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
440 * @ssp: pointer to a struct sifive_serial_port
444 * SiFive UART described by @ssp and program it into the UART. There may
448 static void __ssp_update_baud_rate(struct sifive_serial_port *ssp,
451 if (ssp->baud_rate == rate)
454 ssp->baud_rate = rate;
455 __ssp_update_div(ssp);
460 * @ssp: pointer to a struct sifive_serial_port
463 * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
465 static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop)
474 v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
477 __ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
482 * @ssp: pointer to a struct sifive_serial_port
484 * Delay while the UART TX FIFO referred to by @ssp is marked as full.
488 static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp)
490 while (sifive_serial_is_txfifo_full(ssp))
500 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
502 __ssp_disable_txwm(ssp);
507 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
509 __ssp_disable_rxwm(ssp);
514 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
516 __ssp_enable_txwm(ssp);
521 struct sifive_serial_port *ssp = dev_id;
524 spin_lock(&ssp->port.lock);
526 ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS);
528 spin_unlock(&ssp->port.lock);
533 __ssp_receive_chars(ssp);
535 __ssp_transmit_chars(ssp);
537 spin_unlock(&ssp->port.lock);
564 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
566 __ssp_enable_rxwm(ssp);
573 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
575 __ssp_disable_rxwm(ssp);
576 __ssp_disable_txwm(ssp);
596 struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb);
605 __ssp_wait_for_xmitr(ssp);
615 udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
618 if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {
619 ssp->port.uartclk = cnd->new_rate;
620 __ssp_update_div(ssp);
630 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
637 dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
642 dev_err_once(ssp->port.dev, "parity checking not supported\n");
644 dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
649 __ssp_set_stop_bits(ssp, nstop);
653 ssp->port.uartclk / 16);
654 __ssp_update_baud_rate(ssp, rate);
656 spin_lock_irqsave(&ssp->port.lock, flags);
661 ssp->port.read_status_mask = 0;
664 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
671 __ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
673 spin_unlock_irqrestore(&ssp->port.lock, flags);
687 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
689 ssp->port.type = PORT_SIFIVE_V0;
706 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
709 ch = __ssp_receive_char(ssp, &is_empty);
719 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
721 __ssp_wait_for_xmitr(ssp);
722 __ssp_transmit_char(ssp, c);
777 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
779 __ssp_wait_for_xmitr(ssp);
780 __ssp_transmit_char(ssp, ch);
786 struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
791 if (!ssp)
795 if (ssp->port.sysrq)
798 locked = spin_trylock(&ssp->port.lock);
800 spin_lock(&ssp->port.lock);
802 ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
803 __ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
805 uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);
807 __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
810 spin_unlock(&ssp->port.lock);
816 struct sifive_serial_port *ssp;
825 ssp = sifive_serial_console_ports[co->index];
826 if (!ssp)
832 return uart_set_options(&ssp->port, co, baud, parity, bits, flow);
855 static void __ssp_add_console_port(struct sifive_serial_port *ssp)
857 sifive_serial_console_ports[ssp->port.line] = ssp;
860 static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
862 sifive_serial_console_ports[ssp->port.line] = NULL;
871 static void __ssp_add_console_port(struct sifive_serial_port *ssp)
873 static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
910 struct sifive_serial_port *ssp;
943 ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
944 if (!ssp)
947 ssp->port.dev = &pdev->dev;
948 ssp->port.type = PORT_SIFIVE_V0;
949 ssp->port.iotype = UPIO_MEM;
950 ssp->port.irq = irq;
951 ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;
952 ssp->port.ops = &sifive_serial_uops;
953 ssp->port.line = id;
954 ssp->port.mapbase = mem->start;
955 ssp->port.membase = base;
956 ssp->dev = &pdev->dev;
957 ssp->clk = clk;
958 ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;
960 r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);
968 ssp->port.uartclk = clk_get_rate(ssp->clk);
969 ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
970 __ssp_update_div(ssp);
972 platform_set_drvdata(pdev, ssp);
977 SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
982 SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
984 r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,
985 dev_name(&pdev->dev), ssp);
991 __ssp_add_console_port(ssp);
993 r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);
1002 __ssp_remove_console_port(ssp);
1003 free_irq(ssp->port.irq, ssp);
1005 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1012 struct sifive_serial_port *ssp = platform_get_drvdata(dev);
1014 __ssp_remove_console_port(ssp);
1015 uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);
1016 free_irq(ssp->port.irq, ssp);
1017 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1024 struct sifive_serial_port *ssp = dev_get_drvdata(dev);
1026 return uart_suspend_port(&sifive_serial_uart_driver, &ssp->port);
1031 struct sifive_serial_port *ssp = dev_get_drvdata(dev);
1033 return uart_resume_port(&sifive_serial_uart_driver, &ssp->port);