Lines Matching refs:port
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
118 struct uart_port port;
171 return container_of(uart, struct sci_port, port);
176 * Common SCI definitions, dependent on the port's regshift
501 * value relative to the port mapping rather than the fixed offset
503 * register map for the given port.
535 if (!sci_port->port.dev)
538 pm_runtime_get_sync(sci_port->port.dev);
544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
551 if (!sci_port->port.dev)
557 pm_runtime_put_sync(sci_port->port.dev);
560 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
564 * special-casing the port type, we check the port initialization
569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
572 static void sci_start_tx(struct uart_port *port)
574 struct sci_port *s = to_sci_port(port);
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
579 u16 new, scr = serial_port_in(port, SCSCR);
585 serial_port_out(port, SCSCR, new);
588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
602 ctrl = serial_port_in(port, SCSCR);
609 if (port->type == PORT_SCI)
612 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
616 static void sci_stop_tx(struct uart_port *port)
621 ctrl = serial_port_in(port, SCSCR);
623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
628 serial_port_out(port, SCSCR, ctrl);
631 if (to_sci_port(port)->chan_tx &&
632 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
633 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
634 to_sci_port(port)->cookie_tx = -EINVAL;
639 static void sci_start_rx(struct uart_port *port)
643 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
648 serial_port_out(port, SCSCR, ctrl);
651 static void sci_stop_rx(struct uart_port *port)
655 ctrl = serial_port_in(port, SCSCR);
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
660 ctrl &= ~port_rx_irq_mask(port);
662 serial_port_out(port, SCSCR, ctrl);
665 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
667 if (port->type == PORT_SCI) {
669 serial_port_out(port, SCxSR, mask);
670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
673 serial_port_out(port, SCxSR,
674 serial_port_in(port, SCxSR) & mask);
677 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
685 static int sci_poll_get_char(struct uart_port *port)
691 status = serial_port_in(port, SCxSR);
692 if (status & SCxSR_ERRORS(port)) {
693 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
699 if (!(status & SCxSR_RDxF(port)))
702 c = serial_port_in(port, SCxRDR);
705 serial_port_in(port, SCxSR);
706 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
712 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
717 status = serial_port_in(port, SCxSR);
718 } while (!(status & SCxSR_TDxE(port)));
720 serial_port_out(port, SCxTDR, c);
721 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
726 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
728 struct sci_port *s = to_sci_port(port);
731 * Use port-specific handler if provided.
734 s->cfg->ops->init_pins(port, cflag);
738 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
739 u16 data = serial_port_in(port, SCPDR);
740 u16 ctrl = serial_port_in(port, SCPCR);
744 if (to_sci_port(port)->has_rtscts) {
746 if (!(port->mctrl & TIOCM_RTS)) {
759 serial_port_out(port, SCPDR, data);
760 serial_port_out(port, SCPCR, ctrl);
761 } else if (sci_getreg(port, SCSPTR)->size) {
762 u16 status = serial_port_in(port, SCSPTR);
766 if (!(port->mctrl & TIOCM_RTS))
772 serial_port_out(port, SCSPTR, status);
776 static int sci_txfill(struct uart_port *port)
778 struct sci_port *s = to_sci_port(port);
782 reg = sci_getreg(port, SCTFDR);
784 return serial_port_in(port, SCTFDR) & fifo_mask;
786 reg = sci_getreg(port, SCFDR);
788 return serial_port_in(port, SCFDR) >> 8;
790 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
793 static int sci_txroom(struct uart_port *port)
795 return port->fifosize - sci_txfill(port);
798 static int sci_rxfill(struct uart_port *port)
800 struct sci_port *s = to_sci_port(port);
804 reg = sci_getreg(port, SCRFDR);
806 return serial_port_in(port, SCRFDR) & fifo_mask;
808 reg = sci_getreg(port, SCFDR);
810 return serial_port_in(port, SCFDR) & fifo_mask;
812 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
819 static void sci_transmit_chars(struct uart_port *port)
821 struct circ_buf *xmit = &port->state->xmit;
822 unsigned int stopped = uart_tx_stopped(port);
827 status = serial_port_in(port, SCxSR);
828 if (!(status & SCxSR_TDxE(port))) {
829 ctrl = serial_port_in(port, SCSCR);
834 serial_port_out(port, SCSCR, ctrl);
838 count = sci_txroom(port);
843 if (port->x_char) {
844 c = port->x_char;
845 port->x_char = 0;
849 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) {
850 ctrl = serial_port_in(port, SCSCR);
852 serial_port_out(port, SCSCR, ctrl);
858 serial_port_out(port, SCxTDR, c);
860 port->icount.tx++;
863 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
866 uart_write_wakeup(port);
868 if (port->type == PORT_SCI) {
869 ctrl = serial_port_in(port, SCSCR);
872 serial_port_out(port, SCSCR, ctrl);
875 sci_stop_tx(port);
879 static void sci_receive_chars(struct uart_port *port)
881 struct tty_port *tport = &port->state->port;
886 status = serial_port_in(port, SCxSR);
887 if (!(status & SCxSR_RDxF(port)))
892 count = tty_buffer_request_room(tport, sci_rxfill(port));
898 if (port->type == PORT_SCI) {
899 char c = serial_port_in(port, SCxRDR);
900 if (uart_handle_sysrq_char(port, c))
908 if (port->type == PORT_SCIF ||
909 port->type == PORT_HSCIF) {
910 status = serial_port_in(port, SCxSR);
911 c = serial_port_in(port, SCxRDR);
913 c = serial_port_in(port, SCxRDR);
914 status = serial_port_in(port, SCxSR);
916 if (uart_handle_sysrq_char(port, c)) {
922 if (status & SCxSR_FER(port)) {
924 port->icount.frame++;
925 } else if (status & SCxSR_PER(port)) {
927 port->icount.parity++;
935 serial_port_in(port, SCxSR); /* dummy read */
936 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
939 port->icount.rx += count;
947 serial_port_in(port, SCxRDR);
948 serial_port_in(port, SCxSR); /* dummy read */
949 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
953 static int sci_handle_errors(struct uart_port *port)
956 unsigned short status = serial_port_in(port, SCxSR);
957 struct tty_port *tport = &port->state->port;
958 struct sci_port *s = to_sci_port(port);
962 port->icount.overrun++;
969 if (status & SCxSR_FER(port)) {
971 port->icount.frame++;
977 if (status & SCxSR_PER(port)) {
979 port->icount.parity++;
991 static int sci_handle_fifo_overrun(struct uart_port *port)
993 struct tty_port *tport = &port->state->port;
994 struct sci_port *s = to_sci_port(port);
999 reg = sci_getreg(port, s->params->overrun_reg);
1003 status = serial_port_in(port, s->params->overrun_reg);
1006 serial_port_out(port, s->params->overrun_reg, status);
1008 port->icount.overrun++;
1018 static int sci_handle_breaks(struct uart_port *port)
1021 unsigned short status = serial_port_in(port, SCxSR);
1022 struct tty_port *tport = &port->state->port;
1024 if (uart_handle_break(port))
1027 if (status & SCxSR_BRK(port)) {
1028 port->icount.brk++;
1038 copied += sci_handle_fifo_overrun(port);
1043 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1047 if (rx_trig >= port->fifosize)
1048 rx_trig = port->fifosize - 1;
1053 if (sci_getreg(port, HSRTRGR)->size) {
1054 serial_port_out(port, HSRTRGR, rx_trig);
1058 switch (port->type) {
1095 serial_port_out(port, SCFCR,
1096 (serial_port_in(port, SCFCR) &
1102 static int scif_rtrg_enabled(struct uart_port *port)
1104 if (sci_getreg(port, HSRTRGR)->size)
1105 return serial_port_in(port, HSRTRGR) != 0;
1107 return (serial_port_in(port, SCFCR) &
1114 struct uart_port *port = &s->port;
1116 dev_dbg(port->dev, "Rx timed out\n");
1117 scif_set_rtrg(port, 1);
1123 struct uart_port *port = dev_get_drvdata(dev);
1124 struct sci_port *sci = to_sci_port(port);
1133 struct uart_port *port = dev_get_drvdata(dev);
1134 struct sci_port *sci = to_sci_port(port);
1142 sci->rx_trigger = scif_set_rtrg(port, r);
1143 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1144 scif_set_rtrg(port, 1);
1155 struct uart_port *port = dev_get_drvdata(dev);
1156 struct sci_port *sci = to_sci_port(port);
1159 if (port->type == PORT_HSCIF)
1172 struct uart_port *port = dev_get_drvdata(dev);
1173 struct sci_port *sci = to_sci_port(port);
1181 if (port->type == PORT_HSCIF) {
1187 scif_set_rtrg(port, 1);
1202 struct uart_port *port = &s->port;
1203 struct circ_buf *xmit = &port->state->xmit;
1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1208 spin_lock_irqsave(&port->lock, flags);
1210 uart_xmit_advance(port, s->tx_dma_len);
1213 uart_write_wakeup(port);
1220 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1222 u16 ctrl = serial_port_in(port, SCSCR);
1223 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1232 spin_unlock_irqrestore(&port->lock, flags);
1235 /* Locking: called with port lock held */
1238 struct uart_port *port = &s->port;
1239 struct tty_port *tport = &port->state->port;
1244 port->icount.buf_overrun++;
1246 port->icount.rx += copied;
1295 struct uart_port *port = &s->port;
1298 /* Direct new serial port interrupts back to CPU */
1299 scr = serial_port_in(port, SCSCR);
1300 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1304 scif_set_rtrg(port, s->rx_trigger);
1308 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1315 struct uart_port *port = &s->port;
1320 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1323 spin_lock_irqsave(&port->lock, flags);
1332 tty_flip_buffer_push(&port->state->port);
1350 spin_unlock_irqrestore(&port->lock, flags);
1351 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1356 spin_unlock_irqrestore(&port->lock, flags);
1357 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1359 spin_lock_irqsave(&port->lock, flags);
1363 spin_unlock_irqrestore(&port->lock, flags);
1382 struct uart_port *port = &s->port;
1412 spin_lock_irqsave(&port->lock, flags);
1416 sci_start_rx(port);
1418 spin_unlock_irqrestore(&port->lock, flags);
1427 struct uart_port *port = &s->port;
1428 struct circ_buf *xmit = &port->state->xmit;
1437 * transmit till the end, and then the rest. Take the port lock to get a
1440 spin_lock_irq(&port->lock);
1447 spin_unlock_irq(&port->lock);
1455 spin_unlock_irq(&port->lock);
1456 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1467 spin_unlock_irq(&port->lock);
1468 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1472 spin_unlock_irq(&port->lock);
1473 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1480 spin_lock_irqsave(&port->lock, flags);
1482 sci_start_tx(port);
1483 spin_unlock_irqrestore(&port->lock, flags);
1491 struct uart_port *port = &s->port;
1498 dev_dbg(port->dev, "DMA Rx timed out\n");
1500 spin_lock_irqsave(&port->lock, flags);
1504 spin_unlock_irqrestore(&port->lock, flags);
1510 spin_unlock_irqrestore(&port->lock, flags);
1511 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1528 spin_unlock_irqrestore(&port->lock, flags);
1529 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1540 tty_flip_buffer_push(&port->state->port);
1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1549 spin_unlock_irqrestore(&port->lock, flags);
1554 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1561 chan = dma_request_slave_channel(port->dev,
1564 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1570 cfg.dst_addr = port->mapbase +
1571 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1573 cfg.src_addr = port->mapbase +
1574 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1579 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1587 static void sci_request_dma(struct uart_port *port)
1589 struct sci_port *s = to_sci_port(port);
1592 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1598 if (uart_console(port))
1601 if (!port->dev->of_node)
1610 if (!of_property_present(port->dev->of_node, "dmas"))
1613 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1614 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1618 port->state->xmit.buf,
1622 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1625 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1627 port->state->xmit.buf, &s->tx_dma_addr);
1634 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1635 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1641 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1645 dev_warn(port->dev,
1668 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1674 static void sci_free_dma(struct uart_port *port)
1676 struct sci_port *s = to_sci_port(port);
1684 static void sci_flush_buffer(struct uart_port *port)
1686 struct sci_port *s = to_sci_port(port);
1700 static inline void sci_request_dma(struct uart_port *port)
1704 static inline void sci_free_dma(struct uart_port *port)
1713 struct uart_port *port = ptr;
1714 struct sci_port *s = to_sci_port(port);
1718 u16 scr = serial_port_in(port, SCSCR);
1719 u16 ssr = serial_port_in(port, SCxSR);
1722 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1726 scif_set_rtrg(port, 1);
1737 serial_port_out(port, SCSCR, scr);
1739 serial_port_out(port, SCxSR,
1740 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1741 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1752 if (!scif_rtrg_enabled(port))
1753 scif_set_rtrg(port, s->rx_trigger);
1763 sci_receive_chars(port);
1770 struct uart_port *port = ptr;
1773 spin_lock_irqsave(&port->lock, flags);
1774 sci_transmit_chars(port);
1775 spin_unlock_irqrestore(&port->lock, flags);
1782 struct uart_port *port = ptr;
1786 if (port->type != PORT_SCI)
1789 spin_lock_irqsave(&port->lock, flags);
1790 ctrl = serial_port_in(port, SCSCR);
1792 serial_port_out(port, SCSCR, ctrl);
1793 spin_unlock_irqrestore(&port->lock, flags);
1800 struct uart_port *port = ptr;
1803 sci_handle_breaks(port);
1806 serial_port_in(port, SCxRDR);
1808 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1815 struct uart_port *port = ptr;
1816 struct sci_port *s = to_sci_port(port);
1820 unsigned short ssr_status = serial_port_in(port, SCxSR);
1823 if (ssr_status & SCxSR_BRK(port))
1827 if (!(ssr_status & SCxSR_ERRORS(port)))
1832 if (port->type == PORT_SCI) {
1833 if (sci_handle_errors(port)) {
1835 serial_port_in(port, SCxSR);
1836 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1839 sci_handle_fifo_overrun(port);
1841 sci_receive_chars(port);
1844 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1856 struct uart_port *port = ptr;
1857 struct sci_port *s = to_sci_port(port);
1860 ssr_status = serial_port_in(port, SCxSR);
1861 scr_status = serial_port_in(port, SCSCR);
1864 else if (sci_getreg(port, s->params->overrun_reg)->size)
1865 orer_status = serial_port_in(port, s->params->overrun_reg);
1867 err_enabled = scr_status & port_rx_irq_mask(port);
1870 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1878 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1883 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1888 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1893 sci_handle_fifo_overrun(port);
1946 static int sci_request_irq(struct sci_port *port)
1948 struct uart_port *up = &port->port;
1957 if (port->irqs[w] == port->irqs[i])
1962 if (SCIx_IRQ_IS_MUXED(port)) {
1966 irq = port->irqs[i];
1969 * Certain port types won't support all of the
1977 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1979 if (!port->irqstr[j]) {
1985 port->irqstr[j], port);
1996 free_irq(port->irqs[i], port);
2000 kfree(port->irqstr[j]);
2005 static void sci_free_irq(struct sci_port *port)
2014 int irq = port->irqs[i];
2017 * Certain port types won't support all of the available
2025 if (port->irqs[j] == irq)
2030 free_irq(port->irqs[i], port);
2031 kfree(port->irqstr[i]);
2033 if (SCIx_IRQ_IS_MUXED(port)) {
2040 static unsigned int sci_tx_empty(struct uart_port *port)
2042 unsigned short status = serial_port_in(port, SCxSR);
2043 unsigned short in_tx_fifo = sci_txfill(port);
2045 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2048 static void sci_set_rts(struct uart_port *port, bool state)
2050 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2051 u16 data = serial_port_in(port, SCPDR);
2058 serial_port_out(port, SCPDR, data);
2061 serial_port_out(port, SCPCR,
2062 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2063 } else if (sci_getreg(port, SCSPTR)->size) {
2064 u16 ctrl = serial_port_in(port, SCSPTR);
2071 serial_port_out(port, SCSPTR, ctrl);
2075 static bool sci_get_cts(struct uart_port *port)
2077 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2079 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2080 } else if (sci_getreg(port, SCSPTR)->size) {
2082 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2090 * CTS/RTS is supported in hardware by at least one port and controlled
2097 * port types, but not others. For these it's sufficient to test for the
2098 * existence of the support register and simply ignore the port type.
2100 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2102 struct sci_port *s = to_sci_port(port);
2110 reg = sci_getreg(port, SCFCR);
2112 serial_port_out(port, SCFCR,
2113 serial_port_in(port, SCFCR) |
2124 serial_port_out(port, SCFCR,
2125 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2128 sci_set_rts(port, 0);
2130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2132 serial_port_out(port, SCPCR,
2133 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2137 serial_port_out(port, SCFCR,
2138 serial_port_in(port, SCFCR) | SCFCR_MCE);
2141 sci_set_rts(port, 1);
2145 static unsigned int sci_get_mctrl(struct uart_port *port)
2147 struct sci_port *s = to_sci_port(port);
2158 if (sci_get_cts(port))
2171 static void sci_enable_ms(struct uart_port *port)
2173 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2176 static void sci_break_ctl(struct uart_port *port, int break_state)
2181 /* check whether the port has SCSPTR */
2182 if (!sci_getreg(port, SCSPTR)->size) {
2190 spin_lock_irqsave(&port->lock, flags);
2191 scsptr = serial_port_in(port, SCSPTR);
2192 scscr = serial_port_in(port, SCSCR);
2202 serial_port_out(port, SCSPTR, scsptr);
2203 serial_port_out(port, SCSCR, scscr);
2204 spin_unlock_irqrestore(&port->lock, flags);
2207 static int sci_startup(struct uart_port *port)
2209 struct sci_port *s = to_sci_port(port);
2212 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2214 sci_request_dma(port);
2218 sci_free_dma(port);
2225 static void sci_shutdown(struct uart_port *port)
2227 struct sci_port *s = to_sci_port(port);
2231 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2234 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2236 spin_lock_irqsave(&port->lock, flags);
2237 sci_stop_rx(port);
2238 sci_stop_tx(port);
2243 scr = serial_port_in(port, SCSCR);
2244 serial_port_out(port, SCSCR, scr &
2246 spin_unlock_irqrestore(&port->lock, flags);
2250 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2251 port->line);
2259 sci_free_dma(port);
2269 if (s->port.type != PORT_HSCIF)
2284 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2296 if (s->port.type != PORT_HSCIF)
2315 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2329 if (s->port.type != PORT_HSCIF)
2383 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2388 static void sci_reset(struct uart_port *port)
2392 struct sci_port *s = to_sci_port(port);
2394 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2396 reg = sci_getreg(port, SCFCR);
2398 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2400 sci_clear_SCxSR(port,
2401 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2402 SCxSR_BREAK_CLEAR(port));
2403 if (sci_getreg(port, SCLSR)->size) {
2404 status = serial_port_in(port, SCLSR);
2406 serial_port_out(port, SCLSR, status);
2411 scif_set_rtrg(port, 1);
2414 if (port->type == PORT_SCIFA ||
2415 port->type == PORT_SCIFB)
2416 scif_set_rtrg(port, 1);
2418 scif_set_rtrg(port, s->rx_trigger);
2423 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2429 struct sci_port *s = to_sci_port(port);
2450 * earlyprintk comes here early on with port->uartclk set to zero.
2457 if (!port->uartclk) {
2458 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2465 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2475 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2476 port->type != PORT_SCIFB) {
2490 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2506 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2534 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2543 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2544 serial_port_out(port, SCDL, dl);
2545 serial_port_out(port, SCCKS, sccks);
2548 spin_lock_irqsave(&port->lock, flags);
2550 sci_reset(port);
2552 uart_update_timeout(port, termios->c_cflag, baud);
2557 if (sci_getreg(port, SEMR)->size)
2558 serial_port_out(port, SEMR, 0);
2561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2573 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2574 serial_port_out(port, SCSMR, smr_val);
2575 serial_port_out(port, SCBRR, brr);
2576 if (sci_getreg(port, HSSRR)->size) {
2597 serial_port_out(port, HSSRR, hssrr);
2605 smr_val |= serial_port_in(port, SCSMR) &
2607 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2608 serial_port_out(port, SCSMR, smr_val);
2611 sci_init_pins(port, termios->c_cflag);
2613 port->status &= ~UPSTAT_AUTOCTS;
2615 reg = sci_getreg(port, SCFCR);
2617 unsigned short ctrl = serial_port_in(port, SCFCR);
2619 if ((port->flags & UPF_HARD_FLOW) &&
2622 port->status |= UPSTAT_AUTOCTS;
2634 serial_port_out(port, SCFCR, ctrl);
2636 if (port->flags & UPF_HARD_FLOW) {
2638 sci_set_mctrl(port, port->mctrl);
2646 if (port->type != PORT_SCI)
2649 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2651 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2668 sci_start_rx(port);
2670 spin_unlock_irqrestore(&port->lock, flags);
2674 if (UART_ENABLE_MS(port, termios->c_cflag))
2675 sci_enable_ms(port);
2678 static void sci_pm(struct uart_port *port, unsigned int state,
2681 struct sci_port *sci_port = to_sci_port(port);
2693 static const char *sci_type(struct uart_port *port)
2695 switch (port->type) {
2713 static int sci_remap_port(struct uart_port *port)
2715 struct sci_port *sport = to_sci_port(port);
2720 if (port->membase)
2723 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2724 port->membase = ioremap(port->mapbase, sport->reg_size);
2725 if (unlikely(!port->membase)) {
2726 dev_err(port->dev, "can't remap port#%d\n", port->line);
2735 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2741 static void sci_release_port(struct uart_port *port)
2743 struct sci_port *sport = to_sci_port(port);
2745 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2746 iounmap(port->membase);
2747 port->membase = NULL;
2750 release_mem_region(port->mapbase, sport->reg_size);
2753 static int sci_request_port(struct uart_port *port)
2756 struct sci_port *sport = to_sci_port(port);
2759 res = request_mem_region(port->mapbase, sport->reg_size,
2760 dev_name(port->dev));
2762 dev_err(port->dev, "request_mem_region failed.");
2766 ret = sci_remap_port(port);
2775 static void sci_config_port(struct uart_port *port, int flags)
2778 struct sci_port *sport = to_sci_port(port);
2780 port->type = sport->cfg->type;
2781 sci_request_port(port);
2785 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2885 * where this particular port layout originated. This
2895 pr_err("Can't probe register map for given port\n");
2906 struct uart_port *port = &sci_port->port;
2913 port->ops = &sci_uart_ops;
2914 port->iotype = UPIO_MEM;
2915 port->line = index;
2916 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2922 port->mapbase = res->start;
2933 * The fourth interrupt on SCI port is transmit end interrupt, so
2995 port->dev = &dev->dev;
3000 port->type = p->type;
3001 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3002 port->fifosize = sci_port->params->fifosize;
3004 if (port->type == PORT_SCI && !dev->dev.of_node) {
3006 port->regshift = 2;
3008 port->regshift = 1;
3012 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3018 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3019 port->irqflags = 0;
3021 port->serial_in = sci_serial_in;
3022 port->serial_out = sci_serial_out;
3027 static void sci_cleanup_single(struct sci_port *port)
3029 pm_runtime_disable(port->port.dev);
3034 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3036 sci_poll_put_char(port, ch);
3040 * Print a string to the serial port trying not to disturb
3041 * any possible real use of the port...
3047 struct uart_port *port = &sci_port->port;
3052 if (port->sysrq)
3055 locked = spin_trylock_irqsave(&port->lock, flags);
3057 spin_lock_irqsave(&port->lock, flags);
3060 ctrl = serial_port_in(port, SCSCR);
3064 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3066 uart_console_write(port, s, count, serial_console_putchar);
3069 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3070 while ((serial_port_in(port, SCxSR) & bits) != bits)
3074 serial_port_out(port, SCSCR, ctrl);
3077 spin_unlock_irqrestore(&port->lock, flags);
3083 struct uart_port *port;
3097 port = &sci_port->port;
3102 if (!port->ops)
3105 ret = sci_remap_port(port);
3112 return uart_set_options(port, co, baud, parity, bits, flow);
3195 struct sci_port *port = platform_get_drvdata(dev);
3196 unsigned int type = port->port.type; /* uart_remove_... clears it */
3198 sci_ports_in_use &= ~BIT(port->port.line);
3199 uart_remove_one_port(&sci_uart_driver, &port->port);
3201 sci_cleanup_single(port);
3203 if (port->port.fifosize > 1)
3341 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3364 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3374 sciport->port.flags |= UPF_HARD_FLOW;
3377 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3424 if (sp->port.fifosize > 1) {
3429 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3430 sp->port.type == PORT_HSCIF) {
3433 if (sp->port.fifosize > 1) {
3454 uart_suspend_port(&sci_uart_driver, &sport->port);
3464 uart_resume_port(&sci_uart_driver, &sport->port);
3506 if (!device->port.membase)
3509 device->port.serial_in = sci_serial_in;
3510 device->port.serial_out = sci_serial_out;
3511 device->port.type = type;
3512 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3516 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3517 sci_serial_out(&sci_ports[0].port, SCSCR,