Lines Matching defs:tup
151 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
152 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
153 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
156 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
159 return readl(tup->uport.membase + (reg << tup->uport.regshift));
162 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
175 struct tegra_uart_port *tup = to_tegra_uport(u);
186 if (tup->enable_modem_interrupt)
191 static void set_rts(struct tegra_uart_port *tup, bool active)
195 mcr = tup->mcr_shadow;
200 if (mcr != tup->mcr_shadow) {
201 tegra_uart_write(tup, mcr, UART_MCR);
202 tup->mcr_shadow = mcr;
206 static void set_dtr(struct tegra_uart_port *tup, bool active)
210 mcr = tup->mcr_shadow;
215 if (mcr != tup->mcr_shadow) {
216 tegra_uart_write(tup, mcr, UART_MCR);
217 tup->mcr_shadow = mcr;
221 static void set_loopbk(struct tegra_uart_port *tup, bool active)
223 unsigned long mcr = tup->mcr_shadow;
230 if (mcr != tup->mcr_shadow) {
231 tegra_uart_write(tup, mcr, UART_MCR);
232 tup->mcr_shadow = mcr;
238 struct tegra_uart_port *tup = to_tegra_uport(u);
241 tup->rts_active = !!(mctrl & TIOCM_RTS);
242 set_rts(tup, tup->rts_active);
245 set_dtr(tup, enable);
248 set_loopbk(tup, enable);
253 struct tegra_uart_port *tup = to_tegra_uport(u);
256 lcr = tup->lcr_shadow;
261 tegra_uart_write(tup, lcr, UART_LCR);
262 tup->lcr_shadow = lcr;
268 * @tup: Tegra serial port data structure.
274 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
277 if (tup->current_baud)
278 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
282 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
285 if (tup->current_baud)
286 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
287 tup->current_baud));
290 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
296 iir = tegra_uart_read(tup, UART_IIR);
305 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
307 unsigned long fcr = tup->fcr_shadow;
310 if (tup->rts_active)
311 set_rts(tup, false);
313 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
315 tegra_uart_write(tup, fcr, UART_FCR);
318 tegra_uart_write(tup, fcr, UART_FCR);
321 tegra_uart_write(tup, fcr, UART_FCR);
323 tegra_uart_write(tup, fcr, UART_FCR);
324 if (tup->cdata->fifo_mode_enable_status)
325 tegra_uart_wait_fifo_mode_enabled(tup);
329 tegra_uart_read(tup, UART_SCR);
336 tegra_uart_wait_cycle_time(tup, 32);
339 lsr = tegra_uart_read(tup, UART_LSR);
345 if (tup->rts_active)
346 set_rts(tup, true);
349 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
354 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
355 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
356 baud <= tup->baud_tolerance[i].upper_range_baud)
358 tup->baud_tolerance[i].tolerance) / 10000);
364 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
368 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
369 / tup->required_rate;
370 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
371 diff > (tup->cdata->error_tolerance_high_range * 100)) {
372 dev_err(tup->uport.dev,
380 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
388 if (tup->current_baud == baud)
391 if (tup->cdata->support_clk_src_div) {
393 tup->required_rate = rate;
395 if (tup->n_adjustable_baud_rates)
396 rate = tegra_get_tolerance_rate(tup, baud, rate);
398 ret = clk_set_rate(tup->uart_clk, rate);
400 dev_err(tup->uport.dev,
404 tup->configured_rate = clk_get_rate(tup->uart_clk);
406 ret = tegra_check_rate_in_range(tup);
410 rate = clk_get_rate(tup->uart_clk);
414 spin_lock_irqsave(&tup->uport.lock, flags);
415 lcr = tup->lcr_shadow;
417 tegra_uart_write(tup, lcr, UART_LCR);
419 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
420 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
423 tegra_uart_write(tup, lcr, UART_LCR);
426 tegra_uart_read(tup, UART_SCR);
427 spin_unlock_irqrestore(&tup->uport.lock, flags);
429 tup->current_baud = baud;
432 tegra_uart_wait_sym_time(tup, 2);
436 static u8 tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
445 tup->uport.icount.overrun++;
446 dev_dbg(tup->uport.dev, "Got overrun errors\n");
450 tup->uport.icount.parity++;
451 dev_dbg(tup->uport.dev, "Got Parity errors\n");
454 tup->uport.icount.frame++;
455 dev_dbg(tup->uport.dev, "Got frame errors\n");
462 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
463 if (tup->uport.ignore_status_mask & UART_LSR_BI)
466 tup->uport.icount.brk++;
467 dev_dbg(tup->uport.dev, "Got Break\n");
469 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
485 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
487 struct circ_buf *xmit = &tup->uport.state->xmit;
492 if (tup->cdata->tx_fifo_full_status) {
493 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
497 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
498 uart_xmit_advance(&tup->uport, 1);
502 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
508 tup->tx_in_progress = TEGRA_UART_TX_PIO;
509 tup->tx_bytes = bytes;
510 tup->ier_shadow |= UART_IER_THRI;
511 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
516 struct tegra_uart_port *tup = args;
517 struct circ_buf *xmit = &tup->uport.state->xmit;
522 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
523 count = tup->tx_bytes_requested - state.residue;
524 async_tx_ack(tup->tx_dma_desc);
525 spin_lock_irqsave(&tup->uport.lock, flags);
526 uart_xmit_advance(&tup->uport, count);
527 tup->tx_in_progress = 0;
529 uart_write_wakeup(&tup->uport);
530 tegra_uart_start_next_tx(tup);
531 spin_unlock_irqrestore(&tup->uport.lock, flags);
534 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
537 struct circ_buf *xmit = &tup->uport.state->xmit;
540 tup->tx_bytes = count & ~(0xF);
541 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
543 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
544 tup->tx_bytes, DMA_TO_DEVICE);
546 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
547 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
549 if (!tup->tx_dma_desc) {
550 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
554 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
555 tup->tx_dma_desc->callback_param = tup;
556 tup->tx_in_progress = TEGRA_UART_TX_DMA;
557 tup->tx_bytes_requested = tup->tx_bytes;
558 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
559 dma_async_issue_pending(tup->tx_dma_chan);
563 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
567 struct circ_buf *xmit = &tup->uport.state->xmit;
569 if (!tup->current_baud)
577 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
578 tegra_uart_start_pio_tx(tup, count);
580 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
582 tegra_uart_start_tx_dma(tup, count);
588 struct tegra_uart_port *tup = to_tegra_uport(u);
591 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
592 tegra_uart_start_next_tx(tup);
597 struct tegra_uart_port *tup = to_tegra_uport(u);
602 if (!tup->tx_in_progress) {
603 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
613 struct tegra_uart_port *tup = to_tegra_uport(u);
617 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
620 dmaengine_pause(tup->tx_dma_chan);
621 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
622 dmaengine_terminate_all(tup->tx_dma_chan);
623 count = tup->tx_bytes_requested - state.residue;
624 async_tx_ack(tup->tx_dma_desc);
625 uart_xmit_advance(&tup->uport, count);
626 tup->tx_in_progress = 0;
629 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
631 struct circ_buf *xmit = &tup->uport.state->xmit;
633 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
634 tup->tx_in_progress = 0;
636 uart_write_wakeup(&tup->uport);
637 tegra_uart_start_next_tx(tup);
640 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
647 lsr = tegra_uart_read(tup, UART_LSR);
651 flag = tegra_uart_decode_rx_error(tup, lsr);
655 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
656 tup->uport.icount.rx++;
658 if (uart_handle_sysrq_char(&tup->uport, ch))
661 if (tup->uport.ignore_status_mask & UART_LSR_DR)
668 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
678 tup->uport.icount.rx += count;
680 if (tup->uport.ignore_status_mask & UART_LSR_DR)
683 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
686 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
689 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
691 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
695 static void do_handle_rx_pio(struct tegra_uart_port *tup)
697 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
698 struct tty_port *port = &tup->uport.state->port;
700 tegra_uart_handle_rx_pio(tup, port);
707 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
710 struct tty_port *port = &tup->uport.state->port;
713 async_tx_ack(tup->rx_dma_desc);
714 count = tup->rx_bytes_requested - residue;
717 tegra_uart_copy_rx_to_tty(tup, port, count);
719 do_handle_rx_pio(tup);
724 struct tegra_uart_port *tup = args;
725 struct uart_port *u = &tup->uport;
732 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
735 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
740 if (tup->rts_active)
741 set_rts(tup, false);
743 tup->rx_dma_active = false;
744 tegra_uart_rx_buffer_push(tup, 0);
745 tegra_uart_start_rx_dma(tup);
748 if (tup->rts_active)
749 set_rts(tup, true);
755 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
759 if (!tup->rx_dma_active) {
760 do_handle_rx_pio(tup);
764 dmaengine_pause(tup->rx_dma_chan);
765 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
766 dmaengine_terminate_all(tup->rx_dma_chan);
768 tegra_uart_rx_buffer_push(tup, state.residue);
769 tup->rx_dma_active = false;
772 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
775 if (tup->rts_active)
776 set_rts(tup, false);
778 tegra_uart_terminate_rx_dma(tup);
780 if (tup->rts_active)
781 set_rts(tup, true);
784 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
788 if (tup->rx_dma_active)
791 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
792 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
794 if (!tup->rx_dma_desc) {
795 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
799 tup->rx_dma_active = true;
800 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
801 tup->rx_dma_desc->callback_param = tup;
802 tup->rx_bytes_requested = count;
803 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
804 dma_async_issue_pending(tup->rx_dma_chan);
810 struct tegra_uart_port *tup = to_tegra_uport(u);
813 msr = tegra_uart_read(tup, UART_MSR);
818 tup->uport.icount.rng++;
820 tup->uport.icount.dsr++;
823 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
826 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
831 struct tegra_uart_port *tup = data;
832 struct uart_port *u = &tup->uport;
841 iir = tegra_uart_read(tup, UART_IIR);
843 if (!tup->use_rx_pio && is_rx_int) {
844 tegra_uart_handle_rx_dma(tup);
845 if (tup->rx_in_progress) {
846 ier = tup->ier_shadow;
849 tup->ier_shadow = ier;
850 tegra_uart_write(tup, ier, UART_IER);
853 tegra_uart_start_rx_dma(tup);
865 tup->ier_shadow &= ~UART_IER_THRI;
866 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
867 tegra_uart_handle_tx_pio(tup);
872 if (!tup->use_rx_pio) {
873 is_rx_int = tup->rx_in_progress;
875 ier = tup->ier_shadow;
878 tup->ier_shadow = ier;
879 tegra_uart_write(tup, ier, UART_IER);
884 if (!tup->use_rx_pio) {
885 is_rx_start = tup->rx_in_progress;
886 tup->ier_shadow &= ~UART_IER_RDI;
887 tegra_uart_write(tup, tup->ier_shadow,
890 do_handle_rx_pio(tup);
895 tegra_uart_decode_rx_error(tup,
896 tegra_uart_read(tup, UART_LSR));
908 struct tegra_uart_port *tup = to_tegra_uport(u);
909 struct tty_port *port = &tup->uport.state->port;
912 if (tup->rts_active)
913 set_rts(tup, false);
915 if (!tup->rx_in_progress)
918 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
920 ier = tup->ier_shadow;
923 tup->ier_shadow = ier;
924 tegra_uart_write(tup, ier, UART_IER);
925 tup->rx_in_progress = 0;
927 if (!tup->use_rx_pio)
928 tegra_uart_terminate_rx_dma(tup);
930 tegra_uart_handle_rx_pio(tup, port);
933 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
936 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
937 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
944 tegra_uart_write(tup, 0, UART_IER);
946 lsr = tegra_uart_read(tup, UART_LSR);
948 msr = tegra_uart_read(tup, UART_MSR);
949 mcr = tegra_uart_read(tup, UART_MCR);
951 dev_err(tup->uport.dev,
960 msr = tegra_uart_read(tup, UART_MSR);
961 mcr = tegra_uart_read(tup, UART_MCR);
964 dev_err(tup->uport.dev,
968 lsr = tegra_uart_read(tup, UART_LSR);
972 spin_lock_irqsave(&tup->uport.lock, flags);
974 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
975 tup->current_baud = 0;
976 spin_unlock_irqrestore(&tup->uport.lock, flags);
978 tup->rx_in_progress = 0;
979 tup->tx_in_progress = 0;
981 if (!tup->use_rx_pio)
982 tegra_uart_dma_channel_free(tup, true);
983 if (!tup->use_tx_pio)
984 tegra_uart_dma_channel_free(tup, false);
986 clk_disable_unprepare(tup->uart_clk);
989 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
993 tup->fcr_shadow = 0;
994 tup->mcr_shadow = 0;
995 tup->lcr_shadow = 0;
996 tup->ier_shadow = 0;
997 tup->current_baud = 0;
999 ret = clk_prepare_enable(tup->uart_clk);
1001 dev_err(tup->uport.dev, "could not enable clk\n");
1006 reset_control_assert(tup->rst);
1008 reset_control_deassert(tup->rst);
1010 tup->rx_in_progress = 0;
1011 tup->tx_in_progress = 0;
1031 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1033 if (tup->use_rx_pio) {
1034 tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1036 if (tup->cdata->max_dma_burst_bytes == 8)
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1039 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1042 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1043 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1046 tegra_uart_read(tup, UART_SCR);
1048 if (tup->cdata->fifo_mode_enable_status) {
1049 ret = tegra_uart_wait_fifo_mode_enabled(tup);
1051 clk_disable_unprepare(tup->uart_clk);
1052 dev_err(tup->uport.dev,
1063 tegra_uart_wait_cycle_time(tup, 3);
1071 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1073 clk_disable_unprepare(tup->uart_clk);
1074 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1077 if (!tup->use_rx_pio) {
1078 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1079 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1080 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1082 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1084 tup->rx_in_progress = 1;
1100 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1106 if (!tup->use_rx_pio)
1107 tup->ier_shadow |= TEGRA_UART_IER_EORD;
1109 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1113 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1117 dmaengine_terminate_all(tup->rx_dma_chan);
1118 dma_release_channel(tup->rx_dma_chan);
1119 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1120 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1121 tup->rx_dma_chan = NULL;
1122 tup->rx_dma_buf_phys = 0;
1123 tup->rx_dma_buf_virt = NULL;
1125 dmaengine_terminate_all(tup->tx_dma_chan);
1126 dma_release_channel(tup->tx_dma_chan);
1127 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1129 tup->tx_dma_chan = NULL;
1130 tup->tx_dma_buf_phys = 0;
1131 tup->tx_dma_buf_virt = NULL;
1135 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1144 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1147 dev_err(tup->uport.dev,
1153 dma_buf = dma_alloc_coherent(tup->uport.dev,
1157 dev_err(tup->uport.dev,
1162 dma_sync_single_for_device(tup->uport.dev, dma_phys,
1165 dma_sconfig.src_addr = tup->uport.mapbase;
1167 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1168 tup->rx_dma_chan = dma_chan;
1169 tup->rx_dma_buf_virt = dma_buf;
1170 tup->rx_dma_buf_phys = dma_phys;
1172 dma_phys = dma_map_single(tup->uport.dev,
1173 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1175 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1176 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1180 dma_buf = tup->uport.state->xmit.buf;
1181 dma_sconfig.dst_addr = tup->uport.mapbase;
1184 tup->tx_dma_chan = dma_chan;
1185 tup->tx_dma_buf_virt = dma_buf;
1186 tup->tx_dma_buf_phys = dma_phys;
1191 dev_err(tup->uport.dev,
1193 tegra_uart_dma_channel_free(tup, dma_to_memory);
1202 struct tegra_uart_port *tup = to_tegra_uport(u);
1205 if (!tup->use_tx_pio) {
1206 ret = tegra_uart_dma_channel_allocate(tup, false);
1214 if (!tup->use_rx_pio) {
1215 ret = tegra_uart_dma_channel_allocate(tup, true);
1223 ret = tegra_uart_hw_init(tup);
1230 dev_name(u->dev), tup);
1238 /* tup->uart_clk is already enabled in tegra_uart_hw_init */
1239 clk_disable_unprepare(tup->uart_clk);
1241 if (!tup->use_rx_pio)
1242 tegra_uart_dma_channel_free(tup, true);
1244 if (!tup->use_tx_pio)
1245 tegra_uart_dma_channel_free(tup, false);
1255 struct tegra_uart_port *tup = to_tegra_uport(u);
1257 tup->tx_bytes = 0;
1258 if (tup->tx_dma_chan)
1259 dmaengine_terminate_all(tup->tx_dma_chan);
1264 struct tegra_uart_port *tup = to_tegra_uport(u);
1266 tegra_uart_hw_deinit(tup);
1267 free_irq(u->irq, tup);
1272 struct tegra_uart_port *tup = to_tegra_uport(u);
1274 if (tup->enable_modem_interrupt) {
1275 tup->ier_shadow |= UART_IER_MSI;
1276 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1284 struct tegra_uart_port *tup = to_tegra_uport(u);
1289 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1291 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1298 if (tup->rts_active)
1299 set_rts(tup, false);
1302 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1303 tegra_uart_read(tup, UART_IER);
1304 tegra_uart_write(tup, 0, UART_IER);
1305 tegra_uart_read(tup, UART_IER);
1308 lcr = tup->lcr_shadow;
1336 tegra_uart_write(tup, lcr, UART_LCR);
1337 tup->lcr_shadow = lcr;
1338 tup->symb_bit = tty_get_frame_size(termios->c_cflag);
1345 ret = tegra_set_baudrate(tup, baud);
1347 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1356 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1357 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1358 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1360 if (tup->rts_active)
1361 set_rts(tup, true);
1363 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1364 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1365 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1372 tegra_uart_read(tup, UART_IER);
1375 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1376 tegra_uart_read(tup, UART_IER);
1378 tup->uport.ignore_status_mask = 0;
1381 tup->uport.ignore_status_mask |= UART_LSR_DR;
1383 tup->uport.ignore_status_mask |= UART_LSR_BI;
1420 struct tegra_uart_port *tup)
1435 tup->uport.line = port;
1437 tup->enable_modem_interrupt = of_property_read_bool(np,
1442 tup->use_rx_pio = true;
1447 tup->use_tx_pio = true;
1453 tup->n_adjustable_baud_rates = n_entries / 3;
1454 tup->baud_tolerance =
1455 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1456 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1457 if (!tup->baud_tolerance)
1466 tup->baud_tolerance[index].lower_range_baud =
1473 tup->baud_tolerance[index].upper_range_baud =
1480 tup->baud_tolerance[index].tolerance =
1484 tup->n_adjustable_baud_rates = 0;
1554 struct tegra_uart_port *tup;
1566 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1567 if (!tup) {
1568 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1572 ret = tegra_uart_parse_dt(pdev, tup);
1576 u = &tup->uport;
1581 tup->cdata = cdata;
1583 platform_set_drvdata(pdev, tup);
1590 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1591 if (IS_ERR(tup->uart_clk))
1592 return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock");
1594 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1595 if (IS_ERR(tup->rst)) {
1597 return PTR_ERR(tup->rst);
1616 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1617 struct uart_port *u = &tup->uport;
1626 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1627 struct uart_port *u = &tup->uport;
1634 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1635 struct uart_port *u = &tup->uport;