Lines Matching refs:se
18 #include <linux/soc/qcom/geni-se.h>
119 struct geni_se se;
196 port->se.base = uport->membase;
493 geni_se_cancel_m_cmd(&port->se);
496 geni_se_abort_m_cmd(&port->se);
599 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr,
605 geni_se_cancel_m_cmd(&port->se);
610 geni_se_abort_m_cmd(&port->se);
638 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail],
677 geni_se_cancel_m_cmd(&port->se);
680 geni_se_abort_m_cmd(&port->se);
729 geni_se_cancel_s_cmd(&port->se);
754 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
772 geni_se_cancel_s_cmd(&port->se);
780 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr,
794 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN);
796 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
817 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE);
829 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
945 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining);
1046 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
1047 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
1048 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
1088 proto = geni_se_read_proto(&port->se);
1121 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1123 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
1124 geni_se_select_mode(&port->se, port->dev_data->mode);
1232 ver = geni_se_get_qup_hw_version(&port->se);
1236 clk_rate = get_clk_div_rate(port->se.clk, baud,
1239 dev_err(port->se.dev,
1245 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",
1260 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1261 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1262 geni_icc_set_bw(&port->se);
1389 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1392 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1396 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1412 struct geni_se se;
1419 memset(&se, 0, sizeof(se));
1420 se.base = uport->membase;
1421 if (geni_se_read_proto(&se) != GENI_SE_UART)
1436 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1438 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1439 geni_se_select_mode(&se, GENI_SE_FIFO);
1451 qcom_geni_serial_enable_early_read(&se, dev->con);
1513 geni_icc_enable(&port->se);
1516 geni_se_resources_on(&port->se);
1519 geni_se_resources_off(&port->se);
1521 geni_icc_disable(&port->se);
1602 port->se.dev = &pdev->dev;
1603 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1604 port->se.clk = devm_clk_get(&pdev->dev, "se");
1605 if (IS_ERR(port->se.clk)) {
1606 ret = PTR_ERR(port->se.clk);
1627 ret = geni_icc_get(&port->se, NULL);
1630 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1631 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1634 ret = geni_icc_set_bw(&port->se);
1659 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1722 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);
1723 geni_icc_set_bw(&port->se);
1737 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1738 geni_icc_set_bw(&port->se);
1754 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1755 geni_icc_set_bw(&port->se);