Lines Matching defs:uport
118 struct uart_port uport;
147 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport)
149 return container_of(uport, struct qcom_geni_serial_port, uport);
154 .uport = {
162 .uport = {
170 .uport = {
180 .uport = {
188 static int qcom_geni_serial_request_port(struct uart_port *uport)
190 struct platform_device *pdev = to_platform_device(uport->dev);
191 struct qcom_geni_serial_port *port = to_dev_port(uport);
193 uport->membase = devm_platform_ioremap_resource(pdev, 0);
194 if (IS_ERR(uport->membase))
195 return PTR_ERR(uport->membase);
196 port->se.base = uport->membase;
200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
203 uport->type = PORT_MSM;
204 qcom_geni_serial_request_port(uport);
208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
213 if (uart_console(uport)) {
216 geni_ios = readl(uport->membase + SE_GENI_IOS);
224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
228 struct qcom_geni_serial_port *port = to_dev_port(uport);
230 if (uart_console(uport))
236 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
241 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
258 static bool qcom_geni_serial_main_active(struct uart_port *uport)
260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE;
263 static bool qcom_geni_serial_secondary_active(struct uart_port *uport)
265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE;
268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
276 struct qcom_geni_private_data *private_data = uport->private_data;
279 port = to_dev_port(uport);
297 reg = readl(uport->membase + offset);
306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
323 writel(M_GENI_CMD_ABORT, uport->membase +
326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
332 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
344 static int qcom_geni_serial_get_char(struct uart_port *uport)
346 struct qcom_geni_private_data *private_data = uport->private_data;
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
376 readl(uport->membase + SE_GENI_RX_FIFOn);
386 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
390 qcom_geni_serial_setup_tx(uport, 1);
391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
393 writel(c, uport->membase + SE_GENI_TX_FIFOn);
394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
395 qcom_geni_serial_poll_tx_done(uport);
400 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
402 struct qcom_geni_private_data *private_data = uport->private_data;
410 uport->membase + SE_GENI_TX_FIFOn);
416 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
419 struct qcom_geni_private_data *private_data = uport->private_data;
433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
434 qcom_geni_serial_setup_tx(uport, bytes_to_send);
445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
449 uart_console_write(uport, s + i, chars_to_write,
451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
460 uport->membase + SE_GENI_TX_FIFOn);
464 qcom_geni_serial_poll_tx_done(uport);
470 struct uart_port *uport;
483 uport = &port->uport;
485 locked = spin_trylock_irqsave(&uport->lock, flags);
487 spin_lock_irqsave(&uport->lock, flags);
489 geni_status = readl(uport->membase + SE_GENI_STATUS);
494 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
497 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
499 writel(M_CMD_ABORT_EN, uport->membase +
502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
508 qcom_geni_serial_poll_tx_done(uport);
510 if (!uart_circ_empty(&uport->state->xmit)) {
511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
513 uport->membase + SE_GENI_M_IRQ_EN);
517 __qcom_geni_serial_console_write(uport, s, count);
520 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
523 spin_unlock_irqrestore(&uport->lock, flags);
526 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
531 struct qcom_geni_serial_port *port = to_dev_port(uport);
533 tport = &uport->state->port;
538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
546 uport->icount.rx++;
549 if (uart_handle_break(uport))
553 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
563 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
569 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
571 struct qcom_geni_serial_port *port = to_dev_port(uport);
572 struct tty_port *tport = &uport->state->port;
577 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
581 uport->icount.rx += ret;
585 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
587 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
590 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport)
592 struct qcom_geni_serial_port *port = to_dev_port(uport);
595 if (!qcom_geni_serial_main_active(uport))
607 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
611 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
614 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set");
615 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
618 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
621 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport)
623 struct qcom_geni_serial_port *port = to_dev_port(uport);
624 struct circ_buf *xmit = &uport->state->xmit;
636 qcom_geni_serial_setup_tx(uport, xmit_size);
641 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret);
642 qcom_geni_serial_stop_tx_dma(uport);
649 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport)
653 if (qcom_geni_serial_main_active(uport) ||
654 !qcom_geni_serial_tx_empty(uport))
657 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
660 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
661 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
664 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport)
667 struct qcom_geni_serial_port *port = to_dev_port(uport);
669 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
671 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
672 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
674 if (!qcom_geni_serial_main_active(uport))
678 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
681 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
683 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
685 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
688 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop)
696 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
709 handle_rx_console(uport, total_bytes, drop);
712 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport)
715 struct qcom_geni_serial_port *port = to_dev_port(uport);
718 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
720 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
722 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
724 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
726 if (!qcom_geni_serial_secondary_active(uport))
730 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
736 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
739 qcom_geni_serial_handle_rx_fifo(uport, true);
740 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
742 if (qcom_geni_serial_secondary_active(uport))
743 qcom_geni_serial_abort_rx(uport);
746 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport)
749 struct qcom_geni_serial_port *port = to_dev_port(uport);
751 if (qcom_geni_serial_secondary_active(uport))
752 qcom_geni_serial_stop_rx_fifo(uport);
756 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
758 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
760 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
762 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
765 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport)
767 struct qcom_geni_serial_port *port = to_dev_port(uport);
769 if (!qcom_geni_serial_secondary_active(uport))
773 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
776 if (qcom_geni_serial_secondary_active(uport))
777 qcom_geni_serial_abort_rx(uport);
786 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport)
788 struct qcom_geni_serial_port *port = to_dev_port(uport);
791 if (qcom_geni_serial_secondary_active(uport))
792 qcom_geni_serial_stop_rx_dma(uport);
800 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
801 qcom_geni_serial_stop_rx_dma(uport);
805 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop)
807 struct qcom_geni_serial_port *port = to_dev_port(uport);
811 if (!qcom_geni_serial_secondary_active(uport))
820 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN);
822 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n");
827 handle_rx_uart(uport, rx_in, drop);
833 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
834 qcom_geni_serial_stop_rx_dma(uport);
838 static void qcom_geni_serial_start_rx(struct uart_port *uport)
840 uport->ops->start_rx(uport);
843 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
845 uport->ops->stop_rx(uport);
848 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
850 uport->ops->stop_tx(uport);
853 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport,
856 struct qcom_geni_serial_port *port = to_dev_port(uport);
857 struct circ_buf *xmit = &uport->state->xmit;
866 uart_xmit_advance(uport, tx_bytes);
868 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
875 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport,
878 struct qcom_geni_serial_port *port = to_dev_port(uport);
879 struct circ_buf *xmit = &uport->state->xmit;
886 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
896 qcom_geni_serial_stop_tx_fifo(uport);
908 qcom_geni_serial_setup_tx(uport, pending);
911 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
914 uport->membase + SE_GENI_M_IRQ_EN);
917 qcom_geni_serial_send_chunk_fifo(uport, chunk);
925 uport->membase + SE_GENI_M_IRQ_CLEAR);
929 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
932 uport->membase + SE_GENI_M_IRQ_EN);
936 uart_write_wakeup(uport);
939 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport)
941 struct qcom_geni_serial_port *port = to_dev_port(uport);
942 struct circ_buf *xmit = &uport->state->xmit;
944 uart_xmit_advance(uport, port->tx_remaining);
950 qcom_geni_serial_start_tx_dma(uport);
953 uart_write_wakeup(uport);
965 struct uart_port *uport = dev;
967 struct tty_port *tport = &uport->state->port;
968 struct qcom_geni_serial_port *port = to_dev_port(uport);
970 if (uport->suspended)
973 spin_lock(&uport->lock);
975 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
976 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
977 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT);
978 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT);
979 geni_status = readl(uport->membase + SE_GENI_STATUS);
980 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN);
981 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
982 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
983 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
984 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR);
985 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR);
991 uport->icount.overrun++;
997 uport->icount.parity++;
1000 uport->icount.brk++;
1006 qcom_geni_serial_handle_tx_dma(uport);
1013 uport->icount.parity++;
1018 uport->icount.brk++;
1021 qcom_geni_serial_handle_rx_dma(uport, drop_rx);
1026 qcom_geni_serial_handle_tx_fifo(uport,
1031 qcom_geni_serial_handle_rx_fifo(uport, drop_rx);
1035 uart_unlock_and_check_sysrq(uport);
1042 struct uart_port *uport;
1045 uport = &port->uport;
1049 uport->fifosize =
1058 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf,
1069 static void qcom_geni_serial_shutdown(struct uart_port *uport)
1071 disable_irq(uport->irq);
1073 if (uart_console(uport))
1076 qcom_geni_serial_stop_tx(uport);
1077 qcom_geni_serial_stop_rx(uport);
1080 static int qcom_geni_serial_port_setup(struct uart_port *uport)
1082 struct qcom_geni_serial_port *port = to_dev_port(uport);
1090 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
1094 qcom_geni_serial_stop_rx(uport);
1100 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
1102 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
1113 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
1119 if (uart_console(uport))
1120 qcom_geni_serial_poll_tx_done(uport);
1125 qcom_geni_serial_start_rx(uport);
1131 static int qcom_geni_serial_startup(struct uart_port *uport)
1134 struct qcom_geni_serial_port *port = to_dev_port(uport);
1137 ret = qcom_geni_serial_port_setup(uport);
1141 enable_irq(uport->irq);
1207 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1220 struct qcom_geni_serial_port *port = to_dev_port(uport);
1225 qcom_geni_serial_stop_rx(uport);
1227 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1248 uport->uartclk = clk_rate;
1250 dev_pm_opp_set_rate(uport->dev, clk_rate);
1265 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1266 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1267 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1268 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1307 uart_update_timeout(uport, termios->c_cflag, baud);
1309 if (!uart_console(uport))
1311 uport->membase + SE_UART_LOOPBACK_CFG);
1312 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1313 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1314 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1315 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1316 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1317 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1318 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1319 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1320 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1322 qcom_geni_serial_start_rx(uport);
1328 struct uart_port *uport;
1345 uport = &port->uport;
1347 if (unlikely(!uport->membase))
1351 ret = qcom_geni_serial_port_setup(uport);
1359 return uart_set_options(uport, co, baud, parity, bits, flow);
1375 struct uart_port *uport = &dev->port;
1380 ch = qcom_geni_serial_get_char(uport);
1405 struct uart_port *uport = &dev->port;
1414 if (!uport->membase)
1417 uport->private_data = &earlycon_private_data;
1420 se.base = uport->membase;
1434 qcom_geni_serial_poll_tx_done(uport);
1435 qcom_geni_serial_abort_rx(uport);
1441 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1442 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1443 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1444 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1445 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1446 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1447 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1503 static void qcom_geni_serial_pm(struct uart_port *uport,
1506 struct qcom_geni_serial_port *port = to_dev_port(uport);
1515 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1520 dev_pm_opp_set_rate(uport->dev, 0);
1569 struct uart_port *uport;
1595 uport = &port->uport;
1597 if (uport->private_data)
1600 uport->dev = &pdev->dev;
1614 uport->mapbase = res->start;
1621 port->rx_buf = devm_kzalloc(uport->dev,
1638 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1640 uart_console(uport) ? "console" : "uart", uport->line);
1647 uport->irq = irq;
1648 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1670 uport->private_data = &port->private_data;
1673 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1674 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1675 IRQF_TRIGGER_HIGH, port->name, uport);
1677 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1681 ret = uart_add_one_port(drv, uport);
1691 uart_remove_one_port(drv, uport);
1706 uart_remove_one_port(drv, &port->uport);
1714 struct uart_port *uport = &port->uport;
1715 struct qcom_geni_private_data *private_data = uport->private_data;
1721 if (uart_console(uport)) {
1725 return uart_suspend_port(private_data->drv, uport);
1732 struct uart_port *uport = &port->uport;
1733 struct qcom_geni_private_data *private_data = uport->private_data;
1735 ret = uart_resume_port(private_data->drv, uport);
1736 if (uart_console(uport)) {
1746 struct uart_port *uport;
1750 uport = &port->uport;
1751 private_data = uport->private_data;
1753 if (uart_console(uport)) {
1756 ret = uart_resume_port(private_data->drv, uport);
1762 qcom_geni_serial_port_setup(uport);