Lines Matching refs:up
52 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
55 return readl(up->port.membase + offset);
58 static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
61 writel(value, up->port.membase + offset);
66 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
68 up->ier |= UART_IER_MSI;
69 serial_out(up, UART_IER, up->ier);
74 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
76 if (up->ier & UART_IER_THRI) {
77 up->ier &= ~UART_IER_THRI;
78 serial_out(up, UART_IER, up->ier);
84 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
86 up->ier &= ~UART_IER_RLSI;
87 up->port.read_status_mask &= ~UART_LSR_DR;
88 serial_out(up, UART_IER, up->ier);
91 static inline void receive_chars(struct uart_pxa_port *up, int *status)
104 up->ier &= ~UART_IER_RTOIE;
105 serial_out(up, UART_IER, up->ier);
107 ch = serial_in(up, UART_RX);
109 up->port.icount.rx++;
118 up->port.icount.brk++;
125 if (uart_handle_break(&up->port))
128 up->port.icount.parity++;
130 up->port.icount.frame++;
132 up->port.icount.overrun++;
137 *status &= up->port.read_status_mask;
140 if (up->port.line == up->port.cons->index) {
142 *status |= up->lsr_break_flag;
143 up->lsr_break_flag = 0;
154 if (uart_handle_sysrq_char(&up->port, ch))
157 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
160 *status = serial_in(up, UART_LSR);
162 tty_flip_buffer_push(&up->port.state->port);
171 up->ier |= UART_IER_RTOIE;
172 serial_out(up, UART_IER, up->ier);
175 static void transmit_chars(struct uart_pxa_port *up)
179 uart_port_tx_limited(&up->port, ch, up->port.fifosize / 2,
181 serial_out(up, UART_TX, ch),
187 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
189 if (!(up->ier & UART_IER_THRI)) {
190 up->ier |= UART_IER_THRI;
191 serial_out(up, UART_IER, up->ier);
195 /* should hold up->port.lock */
196 static inline void check_modem_status(struct uart_pxa_port *up)
200 status = serial_in(up, UART_MSR);
206 up->port.icount.rng++;
208 up->port.icount.dsr++;
210 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
212 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
214 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
222 struct uart_pxa_port *up = dev_id;
225 iir = serial_in(up, UART_IIR);
228 spin_lock(&up->port.lock);
229 lsr = serial_in(up, UART_LSR);
231 receive_chars(up, &lsr);
232 check_modem_status(up);
234 transmit_chars(up);
235 spin_unlock(&up->port.lock);
241 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
245 spin_lock_irqsave(&up->port.lock, flags);
246 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
247 spin_unlock_irqrestore(&up->port.lock, flags);
254 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
258 status = serial_in(up, UART_MSR);
274 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
288 mcr |= up->mcr;
290 serial_out(up, UART_MCR, mcr);
295 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
298 spin_lock_irqsave(&up->port.lock, flags);
300 up->lcr |= UART_LCR_SBC;
302 up->lcr &= ~UART_LCR_SBC;
303 serial_out(up, UART_LCR, up->lcr);
304 spin_unlock_irqrestore(&up->port.lock, flags);
309 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
314 up->mcr |= UART_MCR_AFE;
316 up->mcr = 0;
318 up->port.uartclk = clk_get_rate(up->clk);
323 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
331 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
332 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
334 serial_out(up, UART_FCR, 0);
339 (void) serial_in(up, UART_LSR);
340 (void) serial_in(up, UART_RX);
341 (void) serial_in(up, UART_IIR);
342 (void) serial_in(up, UART_MSR);
347 serial_out(up, UART_LCR, UART_LCR_WLEN8);
349 spin_lock_irqsave(&up->port.lock, flags);
350 up->port.mctrl |= TIOCM_OUT2;
351 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
352 spin_unlock_irqrestore(&up->port.lock, flags);
359 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
360 serial_out(up, UART_IER, up->ier);
365 (void) serial_in(up, UART_LSR);
366 (void) serial_in(up, UART_RX);
367 (void) serial_in(up, UART_IIR);
368 (void) serial_in(up, UART_MSR);
375 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
378 free_irq(up->port.irq, up);
383 up->ier = 0;
384 serial_out(up, UART_IER, 0);
386 spin_lock_irqsave(&up->port.lock, flags);
387 up->port.mctrl &= ~TIOCM_OUT2;
388 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
389 spin_unlock_irqrestore(&up->port.lock, flags);
394 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
395 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
398 serial_out(up, UART_FCR, 0);
405 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
426 if ((up->port.uartclk / quot) < (2400 * 16))
428 else if ((up->port.uartclk / quot) < (230400 * 16))
437 spin_lock_irqsave(&up->port.lock, flags);
443 up->ier |= UART_IER_UUE;
450 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
452 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
454 up->port.read_status_mask |= UART_LSR_BI;
459 up->port.ignore_status_mask = 0;
461 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
463 up->port.ignore_status_mask |= UART_LSR_BI;
469 up->port.ignore_status_mask |= UART_LSR_OE;
476 up->port.ignore_status_mask |= UART_LSR_DR;
481 up->ier &= ~UART_IER_MSI;
482 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
483 up->ier |= UART_IER_MSI;
485 serial_out(up, UART_IER, up->ier);
488 up->mcr |= UART_MCR_AFE;
490 up->mcr &= ~UART_MCR_AFE;
492 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
493 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
499 dll = serial_in(up, UART_DLL);
502 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
503 serial_out(up, UART_LCR, cval); /* reset DLAB */
504 up->lcr = cval; /* Save LCR */
505 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
506 serial_out(up, UART_FCR, fcr);
507 spin_unlock_irqrestore(&up->port.lock, flags);
514 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
517 clk_prepare_enable(up->clk);
519 clk_disable_unprepare(up->clk);
533 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
534 up->port.type = PORT_PXA;
547 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
548 return up->name;
559 static void wait_for_xmitr(struct uart_pxa_port *up)
563 /* Wait up to 10ms for the character(s) to be sent. */
565 status = serial_in(up, UART_LSR);
568 up->lsr_break_flag = UART_LSR_BI;
575 /* Wait up to 1s for flow control if necessary */
576 if (up->port.flags & UPF_CONS_FLOW) {
579 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
586 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
588 wait_for_xmitr(up);
589 serial_out(up, UART_TX, ch);
601 struct uart_pxa_port *up = serial_pxa_ports[co->index];
606 clk_enable(up->clk);
608 if (up->port.sysrq)
611 locked = spin_trylock(&up->port.lock);
613 spin_lock(&up->port.lock);
618 ier = serial_in(up, UART_IER);
619 serial_out(up, UART_IER, UART_IER_UUE);
621 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
627 wait_for_xmitr(up);
628 serial_out(up, UART_IER, ier);
631 spin_unlock(&up->port.lock);
633 clk_disable(up->clk);
645 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
646 unsigned char lsr = serial_in(up, UART_LSR);
649 lsr = serial_in(up, UART_LSR);
651 return serial_in(up, UART_RX);
659 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
664 ier = serial_in(up, UART_IER);
665 serial_out(up, UART_IER, UART_IER_UUE);
667 wait_for_xmitr(up);
671 serial_out(up, UART_TX, c);
677 wait_for_xmitr(up);
678 serial_out(up, UART_IER, ier);
686 struct uart_pxa_port *up;
694 up = serial_pxa_ports[co->index];
695 if (!up)
701 return uart_set_options(&up->port, co, baud, parity, bits, flow);