Lines Matching refs:R5
135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
165 /* Rewrite R3/R5, this time without enables masked. */
167 write_zsreg(uap, R5, regs[R5]);
553 uap->curregs[R5] |= set_bits;
554 uap->curregs[R5] &= ~clear_bits;
556 write_zsreg(uap, R5, uap->curregs[R5]);
558 set_bits, clear_bits, uap->curregs[R5]);
690 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
691 if (new_reg != uap->curregs[R5]) {
692 uap->curregs[R5] = new_reg;
693 write_zsreg(uap, R5, uap->curregs[R5]);
839 uap->curregs[R5] = Tx8 | RTS;
841 uap->curregs[R5] |= DTR;
856 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
869 uap->curregs[R5] |= DTR;
870 write_zsreg(uap, R5, uap->curregs[R5]);
876 uap->curregs[R5] &= ~DTR;
877 write_zsreg(uap, R5, uap->curregs[R5]);
944 uap->curregs[R5] &= ~TxENABLE;
947 uap->curregs[R5] &= ~SND_BRK;
1142 uap->curregs[R5] |= DTR;
1143 write_zsreg(uap, R5, uap->curregs[R5]);
1192 uap->curregs[R5] &= ~DTR;
1193 write_zsreg(uap, R5, uap->curregs[R5]);
1903 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);