Lines Matching refs:sport
79 static inline void pic32_uart_writel(struct pic32_sport *sport,
82 __raw_writel(val, sport->port.membase + reg);
85 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
87 return __raw_readl(sport->port.membase + reg);
129 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
132 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
139 struct pic32_sport *sport = to_pic32_sport(port);
140 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
148 struct pic32_sport *sport = to_pic32_sport(port);
152 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
155 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
162 struct pic32_sport *sport = to_pic32_sport(port);
166 if (!sport->cts_gpiod)
168 else if (gpiod_get_value(sport->cts_gpiod))
183 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
185 if (en && !sport->enable_tx_irq) {
186 enable_irq(sport->irq_tx);
187 sport->enable_tx_irq = true;
188 } else if (!en && sport->enable_tx_irq) {
193 disable_irq_nosync(sport->irq_tx);
194 sport->enable_tx_irq = false;
201 struct pic32_sport *sport = to_pic32_sport(port);
203 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
206 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
210 pic32_wait_deplete_txbuf(sport);
212 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
214 pic32_uart_irqtxen(sport, 0);
220 struct pic32_sport *sport = to_pic32_sport(port);
222 pic32_uart_irqtxen(sport, 1);
223 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
230 struct pic32_sport *sport = to_pic32_sport(port);
233 disable_irq(sport->irq_rx);
236 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
243 struct pic32_sport *sport = to_pic32_sport(port);
249 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
252 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
267 struct pic32_sport *sport = to_pic32_sport(port);
286 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
290 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
302 c = pic32_uart_readl(sport, PIC32_UART_RX);
344 struct pic32_sport *sport = to_pic32_sport(port);
349 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
373 pic32_uart_readl(sport, PIC32_UART_STA))) {
376 pic32_uart_writel(sport, PIC32_UART_TX, c);
394 pic32_uart_irqtxen(sport, 0);
430 struct pic32_sport *sport = to_pic32_sport(port);
432 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
434 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
441 struct pic32_sport *sport = to_pic32_sport(port);
444 pic32_wait_deplete_txbuf(sport);
446 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
448 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
455 struct pic32_sport *sport = to_pic32_sport(port);
462 ret = clk_prepare_enable(sport->clk);
469 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
470 pic32_uart_writel(sport, PIC32_UART_STA, 0);
476 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
486 sport->enable_tx_irq = false;
488 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
490 sport->idx);
491 if (!sport->irq_fault_name) {
496 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
497 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
498 IRQF_NO_THREAD, sport->irq_fault_name, port);
501 __func__, sport->irq_fault, ret,
506 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
508 sport->idx);
509 if (!sport->irq_rx_name) {
514 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
515 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
516 IRQF_NO_THREAD, sport->irq_rx_name, port);
519 __func__, sport->irq_rx, ret,
524 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
526 sport->idx);
527 if (!sport->irq_tx_name) {
532 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
533 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
534 IRQF_NO_THREAD, sport->irq_tx_name, port);
537 __func__, sport->irq_tx, ret,
545 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
549 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
557 enable_irq(sport->irq_rx);
562 free_irq(sport->irq_tx, port);
563 kfree(sport->irq_tx_name);
565 free_irq(sport->irq_rx, port);
566 kfree(sport->irq_rx_name);
568 free_irq(sport->irq_fault, port);
569 kfree(sport->irq_fault_name);
571 clk_disable_unprepare(sport->clk);
579 struct pic32_sport *sport = to_pic32_sport(port);
586 clk_disable_unprepare(sport->clk);
589 free_irq(sport->irq_fault, port);
590 kfree(sport->irq_fault_name);
591 free_irq(sport->irq_tx, port);
592 kfree(sport->irq_tx_name);
593 free_irq(sport->irq_rx, port);
594 kfree(sport->irq_rx_name);
602 struct pic32_sport *sport = to_pic32_sport(port);
614 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
617 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
623 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
625 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
628 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
630 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
634 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
639 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) {
641 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
643 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
645 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
649 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
651 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
653 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
666 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
767 struct pic32_sport *sport = to_pic32_sport(port);
769 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
772 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
776 pic32_wait_deplete_txbuf(sport);
778 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
785 struct pic32_sport *sport = pic32_sports[co->index];
788 uart_console_write(&sport->port, s, count, pic32_console_putchar);
796 struct pic32_sport *sport;
806 sport = pic32_sports[co->index];
807 if (!sport)
810 ret = clk_prepare_enable(sport->clk);
817 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
868 struct pic32_sport *sport;
882 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
883 if (!sport)
886 sport->idx = uart_idx;
887 sport->irq_fault = irq_of_parse_and_map(np, 0);
888 sport->irq_rx = irq_of_parse_and_map(np, 1);
889 sport->irq_tx = irq_of_parse_and_map(np, 2);
890 sport->clk = devm_clk_get(&pdev->dev, NULL);
891 if (IS_ERR(sport->clk))
892 return PTR_ERR(sport->clk);
893 sport->dev = &pdev->dev;
898 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN);
899 if (IS_ERR(sport->cts_gpiod))
900 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n");
901 gpiod_set_consumer_name(sport->cts_gpiod, "CTS");
903 pic32_sports[uart_idx] = sport;
904 port = &sport->port;
911 port->uartclk = clk_get_rate(sport->clk);
926 clk_disable_unprepare(sport->clk);
937 /* automatic unroll of sport and gpios */
944 struct pic32_sport *sport = to_pic32_sport(port);
947 clk_disable_unprepare(sport->clk);
949 pic32_sports[sport->idx] = NULL;
951 /* automatic unroll of sport and gpios */