Lines Matching defs:membase
208 void __iomem *membase;
241 /* protect the eg20t_port private structure and io access to membase */
315 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
317 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
319 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
321 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
323 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
325 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
328 ioread8(priv->membase + PCH_UART_BRCSR));
330 lcr = ioread8(priv->membase + UART_LCR);
331 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
333 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
335 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
336 iowrite8(lcr, priv->membase + UART_LCR);
417 u8 ier = ioread8(priv->membase + UART_IER);
419 iowrite8(ier, priv->membase + UART_IER);
425 u8 ier = ioread8(priv->membase + UART_IER);
427 iowrite8(ier, priv->membase + UART_IER);
467 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
468 iowrite8(dll, priv->membase + PCH_UART_DLL);
469 iowrite8(dlm, priv->membase + PCH_UART_DLM);
470 iowrite8(lcr, priv->membase + UART_LCR);
484 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
486 priv->membase + UART_FCR);
487 iowrite8(priv->fcr, priv->membase + UART_FCR);
536 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
538 priv->membase + UART_FCR);
539 iowrite8(fcr, priv->membase + UART_FCR);
547 unsigned int msr = ioread8(priv->membase + UART_MSR);
559 lsr = ioread8(priv->membase + UART_LSR);
560 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
562 lsr = ioread8(priv->membase + UART_LSR)) {
563 rbr = ioread8(priv->membase + PCH_UART_RBR);
580 return ioread8(priv->membase + UART_IIR) &\
586 return ioread8(priv->membase + UART_LSR);
593 lcr = ioread8(priv->membase + UART_LCR);
599 iowrite8(lcr, priv->membase + UART_LCR);
838 iowrite8(port->x_char, priv->membase + PCH_UART_THR);
846 iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
895 iowrite8(port->x_char, priv->membase + PCH_UART_THR);
1144 iowrite8(mcr, priv->membase + UART_MCR);
1377 pci_iounmap(priv->pdev, priv->membase);
1385 void __iomem *membase;
1392 membase = pci_iomap(priv->pdev, 1, 0);
1393 if (!membase) {
1397 priv->membase = port->membase = membase;
1453 status = ioread8(up->membase + UART_LSR);
1466 unsigned int msr = ioread8(up->membase + UART_MSR);
1485 u8 lsr = ioread8(priv->membase + UART_LSR);
1490 return ioread8(priv->membase + PCH_UART_RBR);
1504 ier = ioread8(priv->membase + UART_IER);
1511 iowrite8(c, priv->membase + PCH_UART_THR);
1518 iowrite8(ier, priv->membase + UART_IER);
1554 iowrite8(ch, priv->membase + PCH_UART_THR);
1593 ier = ioread8(priv->membase + UART_IER);
1604 iowrite8(ier, priv->membase + UART_IER);
1630 if (!port || (!port->iobase && !port->membase))
1723 priv->port.membase = NULL;