Lines Matching refs:port
76 struct uart_port port;
84 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
86 writel(val, port->membase + off);
89 static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
91 return readl(port->membase + off);
94 static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
98 ctl = owl_uart_read(port, OWL_UART_CTL);
105 owl_uart_write(port, ctl, OWL_UART_CTL);
108 static unsigned int owl_uart_get_mctrl(struct uart_port *port)
113 ctl = owl_uart_read(port, OWL_UART_CTL);
114 stat = owl_uart_read(port, OWL_UART_STAT);
122 static unsigned int owl_uart_tx_empty(struct uart_port *port)
128 spin_lock_irqsave(&port->lock, flags);
130 val = owl_uart_read(port, OWL_UART_STAT);
133 spin_unlock_irqrestore(&port->lock, flags);
138 static void owl_uart_stop_rx(struct uart_port *port)
142 val = owl_uart_read(port, OWL_UART_CTL);
144 owl_uart_write(port, val, OWL_UART_CTL);
146 val = owl_uart_read(port, OWL_UART_STAT);
148 owl_uart_write(port, val, OWL_UART_STAT);
151 static void owl_uart_stop_tx(struct uart_port *port)
155 val = owl_uart_read(port, OWL_UART_CTL);
157 owl_uart_write(port, val, OWL_UART_CTL);
159 val = owl_uart_read(port, OWL_UART_STAT);
161 owl_uart_write(port, val, OWL_UART_STAT);
164 static void owl_uart_start_tx(struct uart_port *port)
168 if (uart_tx_stopped(port)) {
169 owl_uart_stop_tx(port);
173 val = owl_uart_read(port, OWL_UART_STAT);
175 owl_uart_write(port, val, OWL_UART_STAT);
177 val = owl_uart_read(port, OWL_UART_CTL);
179 owl_uart_write(port, val, OWL_UART_CTL);
182 static void owl_uart_send_chars(struct uart_port *port)
186 uart_port_tx(port, ch,
187 !(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU),
188 owl_uart_write(port, ch, OWL_UART_TXDAT));
191 static void owl_uart_receive_chars(struct uart_port *port)
195 val = owl_uart_read(port, OWL_UART_CTL);
197 owl_uart_write(port, val, OWL_UART_CTL);
199 stat = owl_uart_read(port, OWL_UART_STAT);
204 port->icount.overrun++;
208 port->icount.brk++;
209 port->icount.frame++;
211 stat &= port->read_status_mask;
215 port->icount.rx++;
217 val = owl_uart_read(port, OWL_UART_RXDAT);
220 if ((stat & port->ignore_status_mask) == 0)
221 tty_insert_flip_char(&port->state->port, val, flag);
223 stat = owl_uart_read(port, OWL_UART_STAT);
226 tty_flip_buffer_push(&port->state->port);
231 struct uart_port *port = dev_id;
235 spin_lock_irqsave(&port->lock, flags);
237 stat = owl_uart_read(port, OWL_UART_STAT);
240 owl_uart_receive_chars(port);
243 owl_uart_send_chars(port);
245 stat = owl_uart_read(port, OWL_UART_STAT);
247 owl_uart_write(port, stat, OWL_UART_STAT);
249 spin_unlock_irqrestore(&port->lock, flags);
254 static void owl_uart_shutdown(struct uart_port *port)
259 spin_lock_irqsave(&port->lock, flags);
261 val = owl_uart_read(port, OWL_UART_CTL);
264 owl_uart_write(port, val, OWL_UART_CTL);
266 spin_unlock_irqrestore(&port->lock, flags);
268 free_irq(port->irq, port);
271 static int owl_uart_startup(struct uart_port *port)
277 ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
278 "owl-uart", port);
282 spin_lock_irqsave(&port->lock, flags);
284 val = owl_uart_read(port, OWL_UART_STAT);
287 owl_uart_write(port, val, OWL_UART_STAT);
289 val = owl_uart_read(port, OWL_UART_CTL);
292 owl_uart_write(port, val, OWL_UART_CTL);
294 spin_unlock_irqrestore(&port->lock, flags);
305 static void owl_uart_set_termios(struct uart_port *port,
309 struct owl_uart_port *owl_port = to_owl_uart_port(port);
314 spin_lock_irqsave(&port->lock, flags);
316 ctl = owl_uart_read(port, OWL_UART_CTL);
359 owl_uart_write(port, ctl, OWL_UART_CTL);
361 baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
368 port->read_status_mask |= OWL_UART_STAT_RXER;
370 port->read_status_mask |= OWL_UART_STAT_RXST;
372 uart_update_timeout(port, termios->c_cflag, baud);
374 spin_unlock_irqrestore(&port->lock, flags);
377 static void owl_uart_release_port(struct uart_port *port)
379 struct platform_device *pdev = to_platform_device(port->dev);
386 if (port->flags & UPF_IOREMAP) {
387 devm_release_mem_region(port->dev, port->mapbase,
389 devm_iounmap(port->dev, port->membase);
390 port->membase = NULL;
394 static int owl_uart_request_port(struct uart_port *port)
396 struct platform_device *pdev = to_platform_device(port->dev);
403 if (!devm_request_mem_region(port->dev, port->mapbase,
404 resource_size(res), dev_name(port->dev)))
407 if (port->flags & UPF_IOREMAP) {
408 port->membase = devm_ioremap(port->dev, port->mapbase,
410 if (!port->membase)
417 static const char *owl_uart_type(struct uart_port *port)
419 return (port->type == PORT_OWL) ? "owl-uart" : NULL;
422 static int owl_uart_verify_port(struct uart_port *port,
425 if (port->type != PORT_OWL)
428 if (port->irq != ser->irq)
434 static void owl_uart_config_port(struct uart_port *port, int flags)
437 port->type = PORT_OWL;
438 owl_uart_request_port(port);
444 static int owl_uart_poll_get_char(struct uart_port *port)
446 if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM)
449 return owl_uart_read(port, OWL_UART_RXDAT);
452 static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch)
458 ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,
463 dev_err(port->dev, "Timeout waiting while UART TX FULL\n");
467 owl_uart_write(port, ch, OWL_UART_TXDAT);
495 static void owl_console_putchar(struct uart_port *port, unsigned char ch)
497 if (!port->membase)
500 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
503 owl_uart_write(port, ch, OWL_UART_TXDAT);
506 static void owl_uart_port_write(struct uart_port *port, const char *s,
515 if (port->sysrq)
518 locked = spin_trylock(&port->lock);
520 spin_lock(&port->lock);
524 old_ctl = owl_uart_read(port, OWL_UART_CTL);
528 owl_uart_write(port, val, OWL_UART_CTL);
530 uart_console_write(port, s, count, owl_console_putchar);
533 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
537 val = owl_uart_read(port, OWL_UART_STAT);
539 owl_uart_write(port, val, OWL_UART_STAT);
541 owl_uart_write(port, old_ctl, OWL_UART_CTL);
544 spin_unlock(&port->lock);
558 owl_uart_port_write(&owl_port->port, s, count);
573 if (!owl_port || !owl_port->port.membase)
579 return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
606 owl_uart_port_write(&dev->port, s, count);
612 if (!device->port.membase)
681 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
701 owl_port->port.dev = &pdev->dev;
702 owl_port->port.line = pdev->id;
703 owl_port->port.type = PORT_OWL;
704 owl_port->port.iotype = UPIO_MEM;
705 owl_port->port.mapbase = res_mem->start;
706 owl_port->port.irq = irq;
707 owl_port->port.uartclk = clk_get_rate(owl_port->clk);
708 if (owl_port->port.uartclk == 0) {
713 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
714 owl_port->port.x_char = 0;
715 owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
716 owl_port->port.ops = &owl_uart_ops;
721 ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
732 uart_remove_one_port(&owl_uart_driver, &owl_port->port);