Lines Matching refs:up
172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
176 offset <<= up->port.regshift;
177 return readw(up->port.membase + offset);
180 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
182 offset <<= up->port.regshift;
183 writew(value, up->port.membase + offset);
186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
191 serial_out(up, UART_FCR, 0);
195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
202 return pdata->get_context_loss_count(up->dev);
206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
208 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
213 pdata->enable_wakeup(up->dev, enable);
271 struct uart_omap_port *up = to_uart_omap_port(port);
273 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
275 up->ier |= UART_IER_MSI;
276 serial_out(up, UART_IER, up->ier);
281 struct uart_omap_port *up = to_uart_omap_port(port);
286 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
294 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
295 serial_out(up, UART_OMAP_SCR, up->scr);
298 if (gpiod_get_value(up->rts_gpiod) != res) {
302 gpiod_set_value(up->rts_gpiod, res);
313 up->scr |= OMAP_UART_SCR_TX_EMPTY;
314 serial_out(up, UART_OMAP_SCR, up->scr);
319 if (up->ier & UART_IER_THRI) {
320 up->ier &= ~UART_IER_THRI;
321 serial_out(up, UART_IER, up->ier);
327 struct uart_omap_port *up = to_uart_omap_port(port);
329 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
330 up->port.read_status_mask &= ~UART_LSR_DR;
331 serial_out(up, UART_IER, up->ier);
334 static void serial_omap_put_char(struct uart_omap_port *up, unsigned char ch)
336 serial_out(up, UART_TX, ch);
338 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
339 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
340 up->rs485_tx_filter_count++;
343 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
347 uart_port_tx_limited(&up->port, ch, up->port.fifosize / 4,
349 serial_omap_put_char(up, ch),
353 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
355 if (!(up->ier & UART_IER_THRI)) {
356 up->ier |= UART_IER_THRI;
357 serial_out(up, UART_IER, up->ier);
363 struct uart_omap_port *up = to_uart_omap_port(port);
369 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
370 serial_out(up, UART_OMAP_SCR, up->scr);
374 if (gpiod_get_value(up->rts_gpiod) != res) {
375 gpiod_set_value(up->rts_gpiod, res);
383 up->rs485_tx_filter_count = 0;
385 serial_omap_enable_ier_thri(up);
390 struct uart_omap_port *up = to_uart_omap_port(port);
393 spin_lock_irqsave(&up->port.lock, flags);
394 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
395 serial_out(up, UART_IER, up->ier);
396 spin_unlock_irqrestore(&up->port.lock, flags);
401 struct uart_omap_port *up = to_uart_omap_port(port);
404 spin_lock_irqsave(&up->port.lock, flags);
405 up->ier |= UART_IER_RLSI | UART_IER_RDI;
406 serial_out(up, UART_IER, up->ier);
407 spin_unlock_irqrestore(&up->port.lock, flags);
410 static unsigned int check_modem_status(struct uart_omap_port *up)
414 status = serial_in(up, UART_MSR);
415 status |= up->msr_saved_flags;
416 up->msr_saved_flags = 0;
420 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
421 up->port.state != NULL) {
423 up->port.icount.rng++;
425 up->port.icount.dsr++;
428 (&up->port, status & UART_MSR_DCD);
431 (&up->port, status & UART_MSR_CTS);
432 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
438 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
447 serial_in(up, UART_RX);
448 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
449 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
450 up->rs485_tx_filter_count)
451 up->rs485_tx_filter_count--;
454 up->port.icount.rx++;
460 up->port.icount.brk++;
467 if (uart_handle_break(&up->port))
474 up->port.icount.parity++;
479 up->port.icount.frame++;
483 up->port.icount.overrun++;
486 if (up->port.line == up->port.cons->index) {
488 lsr |= up->lsr_break_flag;
491 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
494 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
501 ch = serial_in(up, UART_RX);
502 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
503 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
504 up->rs485_tx_filter_count) {
505 up->rs485_tx_filter_count--;
509 up->port.icount.rx++;
511 if (uart_handle_sysrq_char(&up->port, ch))
514 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, TTY_NORMAL);
524 struct uart_omap_port *up = dev_id;
530 spin_lock(&up->port.lock);
533 iir = serial_in(up, UART_IIR);
538 lsr = serial_in(up, UART_LSR);
545 check_modem_status(up);
548 transmit_chars(up, lsr);
552 serial_omap_rdi(up, lsr);
555 serial_omap_rlsi(up, lsr);
566 spin_unlock(&up->port.lock);
568 tty_flip_buffer_push(&up->port.state->port);
570 up->port_activity = jiffies;
577 struct uart_omap_port *up = to_uart_omap_port(port);
581 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
582 spin_lock_irqsave(&up->port.lock, flags);
583 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
584 spin_unlock_irqrestore(&up->port.lock, flags);
591 struct uart_omap_port *up = to_uart_omap_port(port);
595 status = check_modem_status(up);
597 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
612 struct uart_omap_port *up = to_uart_omap_port(port);
615 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
627 old_mcr = serial_in(up, UART_MCR);
630 up->mcr = old_mcr | mcr;
631 serial_out(up, UART_MCR, up->mcr);
634 lcr = serial_in(up, UART_LCR);
635 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
637 up->efr |= UART_EFR_RTS;
639 up->efr &= ~UART_EFR_RTS;
640 serial_out(up, UART_EFR, up->efr);
641 serial_out(up, UART_LCR, lcr);
646 struct uart_omap_port *up = to_uart_omap_port(port);
649 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
650 spin_lock_irqsave(&up->port.lock, flags);
652 up->lcr |= UART_LCR_SBC;
654 up->lcr &= ~UART_LCR_SBC;
655 serial_out(up, UART_LCR, up->lcr);
656 spin_unlock_irqrestore(&up->port.lock, flags);
661 struct uart_omap_port *up = to_uart_omap_port(port);
668 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
669 up->name, up);
673 /* Optional wake-up IRQ */
674 if (up->wakeirq) {
675 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
677 free_irq(up->port.irq, up);
682 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
684 pm_runtime_get_sync(up->dev);
689 serial_omap_clear_fifos(up);
694 (void) serial_in(up, UART_LSR);
695 if (serial_in(up, UART_LSR) & UART_LSR_DR)
696 (void) serial_in(up, UART_RX);
697 (void) serial_in(up, UART_IIR);
698 (void) serial_in(up, UART_MSR);
703 serial_out(up, UART_LCR, UART_LCR_WLEN8);
704 spin_lock_irqsave(&up->port.lock, flags);
708 up->port.mctrl |= TIOCM_OUT2;
709 serial_omap_set_mctrl(&up->port, up->port.mctrl);
710 spin_unlock_irqrestore(&up->port.lock, flags);
712 up->msr_saved_flags = 0;
718 up->ier = UART_IER_RLSI | UART_IER_RDI;
719 serial_out(up, UART_IER, up->ier);
721 /* Enable module level wake up */
722 up->wer = OMAP_UART_WER_MOD_WKUP;
723 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
724 up->wer |= OMAP_UART_TX_WAKEUP_EN;
726 serial_out(up, UART_OMAP_WER, up->wer);
728 up->port_activity = jiffies;
734 struct uart_omap_port *up = to_uart_omap_port(port);
737 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
742 up->ier = 0;
743 serial_out(up, UART_IER, 0);
745 spin_lock_irqsave(&up->port.lock, flags);
746 up->port.mctrl &= ~TIOCM_OUT2;
747 serial_omap_set_mctrl(&up->port, up->port.mctrl);
748 spin_unlock_irqrestore(&up->port.lock, flags);
753 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
754 serial_omap_clear_fifos(up);
759 if (serial_in(up, UART_LSR) & UART_LSR_DR)
760 (void) serial_in(up, UART_RX);
762 pm_runtime_put_sync(up->dev);
763 free_irq(up->port.irq, up);
764 dev_pm_clear_wake_irq(up->dev);
769 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
772 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
779 struct uart_omap_port *up = to_uart_omap_port(port);
803 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
804 up->latency = up->calc_latency;
805 schedule_work(&up->qos_work);
807 up->dll = quot & 0xff;
808 up->dlh = quot >> 8;
809 up->mdr1 = UART_OMAP_MDR1_DISABLE;
811 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
818 spin_lock_irqsave(&up->port.lock, flags);
825 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
827 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
829 up->port.read_status_mask |= UART_LSR_BI;
834 up->port.ignore_status_mask = 0;
836 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
838 up->port.ignore_status_mask |= UART_LSR_BI;
844 up->port.ignore_status_mask |= UART_LSR_OE;
851 up->port.ignore_status_mask |= UART_LSR_DR;
856 up->ier &= ~UART_IER_MSI;
857 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
858 up->ier |= UART_IER_MSI;
859 serial_out(up, UART_IER, up->ier);
860 serial_out(up, UART_LCR, cval); /* reset DLAB */
861 up->lcr = cval;
862 up->scr = 0;
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
871 serial_out(up, UART_DLL, 0);
872 serial_out(up, UART_DLM, 0);
873 serial_out(up, UART_LCR, 0);
875 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
877 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
878 up->efr &= ~UART_EFR_SCD;
879 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
881 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
882 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
883 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
886 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
900 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
901 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
902 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
905 serial_out(up, UART_FCR, up->fcr);
906 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
908 serial_out(up, UART_OMAP_SCR, up->scr);
911 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
912 serial_out(up, UART_MCR, up->mcr);
913 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
914 serial_out(up, UART_EFR, up->efr);
915 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
919 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
920 serial_omap_mdr1_errataset(up, up->mdr1);
922 serial_out(up, UART_OMAP_MDR1, up->mdr1);
924 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
925 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
927 serial_out(up, UART_LCR, 0);
928 serial_out(up, UART_IER, 0);
929 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
931 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
932 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
934 serial_out(up, UART_LCR, 0);
935 serial_out(up, UART_IER, up->ier);
936 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
938 serial_out(up, UART_EFR, up->efr);
939 serial_out(up, UART_LCR, cval);
942 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
944 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
946 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
947 serial_omap_mdr1_errataset(up, up->mdr1);
949 serial_out(up, UART_OMAP_MDR1, up->mdr1);
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
955 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
956 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
959 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
960 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
961 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
963 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
965 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
967 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
969 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
970 up->efr |= UART_EFR_CTS;
973 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
976 if (up->port.flags & UPF_SOFT_FLOW) {
978 up->efr &= OMAP_UART_SW_CLR;
986 up->efr |= OMAP_UART_SW_RX;
994 up->port.status |= UPSTAT_AUTOXOFF;
995 up->efr |= OMAP_UART_SW_TX;
1005 up->mcr |= UART_MCR_XONANY;
1007 up->mcr &= ~UART_MCR_XONANY;
1009 serial_out(up, UART_MCR, up->mcr);
1010 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1011 serial_out(up, UART_EFR, up->efr);
1012 serial_out(up, UART_LCR, up->lcr);
1014 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1016 spin_unlock_irqrestore(&up->port.lock, flags);
1017 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1024 struct uart_omap_port *up = to_uart_omap_port(port);
1027 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1029 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 efr = serial_in(up, UART_EFR);
1031 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1032 serial_out(up, UART_LCR, 0);
1034 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1035 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1036 serial_out(up, UART_EFR, efr);
1037 serial_out(up, UART_LCR, 0);
1053 struct uart_omap_port *up = to_uart_omap_port(port);
1055 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1056 up->port.line);
1057 up->port.type = PORT_OMAP;
1058 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1072 struct uart_omap_port *up = to_uart_omap_port(port);
1074 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1075 return up->name;
1078 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1082 /* Wait up to 10ms for the character(s) to be sent. */
1084 status = serial_in(up, UART_LSR);
1087 up->lsr_break_flag = UART_LSR_BI;
1094 /* Wait up to 1s for flow control if necessary */
1095 if (up->port.flags & UPF_CONS_FLOW) {
1098 unsigned int msr = serial_in(up, UART_MSR);
1100 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1113 struct uart_omap_port *up = to_uart_omap_port(port);
1115 wait_for_xmitr(up);
1116 serial_out(up, UART_TX, ch);
1121 struct uart_omap_port *up = to_uart_omap_port(port);
1124 status = serial_in(up, UART_LSR);
1130 status = serial_in(up, UART_RX);
1200 struct uart_omap_port *up = to_uart_omap_port(port);
1202 wait_for_xmitr(up);
1203 serial_out(up, UART_TX, ch);
1210 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1216 if (up->port.sysrq)
1219 locked = spin_trylock(&up->port.lock);
1221 spin_lock(&up->port.lock);
1226 ier = serial_in(up, UART_IER);
1227 serial_out(up, UART_IER, 0);
1229 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1235 wait_for_xmitr(up);
1236 serial_out(up, UART_IER, ier);
1244 if (up->msr_saved_flags)
1245 check_modem_status(up);
1248 spin_unlock(&up->port.lock);
1255 struct uart_omap_port *up;
1263 up = serial_omap_console_ports[co->index];
1268 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1281 static void serial_omap_add_console_port(struct uart_omap_port *up)
1283 serial_omap_console_ports[up->port.line] = up;
1292 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1302 struct uart_omap_port *up = to_uart_omap_port(port);
1307 mode = up->ier;
1308 up->ier = 0;
1309 serial_out(up, UART_IER, 0);
1315 gpiod_set_value(up->rts_gpiod, val);
1318 up->ier = mode;
1319 serial_out(up, UART_IER, up->ier);
1325 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1326 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1327 serial_out(up, UART_OMAP_SCR, up->scr);
1370 struct uart_omap_port *up = dev_get_drvdata(dev);
1372 up->is_suspending = true;
1379 struct uart_omap_port *up = dev_get_drvdata(dev);
1381 up->is_suspending = false;
1386 struct uart_omap_port *up = dev_get_drvdata(dev);
1388 uart_suspend_port(&serial_omap_reg, &up->port);
1389 flush_work(&up->qos_work);
1392 serial_omap_enable_wakeup(up, true);
1394 serial_omap_enable_wakeup(up, false);
1401 struct uart_omap_port *up = dev_get_drvdata(dev);
1404 serial_omap_enable_wakeup(up, false);
1406 uart_resume_port(&serial_omap_reg, &up->port);
1415 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1420 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1440 dev_warn(up->dev,
1442 up->name);
1453 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1457 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1459 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1462 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1463 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1493 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1496 struct serial_rs485 *rs485conf = &up->port.rs485;
1502 up->rts_gpiod = NULL;
1507 up->port.rs485_config = serial_omap_config_rs485;
1508 up->port.rs485_supported = serial_omap_rs485_supported;
1510 ret = uart_get_rs485_mode(&up->port);
1525 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1526 if (IS_ERR(up->rts_gpiod)) {
1527 ret = PTR_ERR(up->rts_gpiod);
1531 up->rts_gpiod = NULL;
1532 up->port.rs485_supported = (const struct serial_rs485) { };
1538 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1547 struct uart_omap_port *up;
1568 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1569 if (!up)
1576 up->dev = &pdev->dev;
1577 up->port.dev = &pdev->dev;
1578 up->port.type = PORT_OMAP;
1579 up->port.iotype = UPIO_MEM;
1580 up->port.irq = uartirq;
1581 up->port.regshift = 2;
1582 up->port.fifosize = 64;
1583 up->port.ops = &serial_omap_pops;
1584 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1596 up->port.line = ret;
1598 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1599 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1605 up->wakeirq = wakeirq;
1606 if (!up->wakeirq)
1607 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1608 up->port.line);
1610 sprintf(up->name, "OMAP UART%d", up->port.line);
1611 up->port.mapbase = mem->start;
1612 up->port.membase = base;
1613 up->port.flags = omap_up_info->flags;
1614 up->port.uartclk = omap_up_info->uartclk;
1615 if (!up->port.uartclk) {
1616 up->port.uartclk = DEFAULT_CLK_SPEED;
1622 ret = serial_omap_probe_rs485(up, &pdev->dev);
1626 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1627 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1628 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1629 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1631 platform_set_drvdata(pdev, up);
1635 device_init_wakeup(up->dev, true);
1641 omap_serial_fill_features_erratas(up);
1643 ui[up->port.line] = up;
1644 serial_omap_add_console_port(up);
1646 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1655 cpu_latency_qos_remove_request(&up->pm_qos_request);
1656 device_init_wakeup(up->dev, false);
1664 struct uart_omap_port *up = platform_get_drvdata(dev);
1666 pm_runtime_get_sync(up->dev);
1668 uart_remove_one_port(&serial_omap_reg, &up->port);
1670 pm_runtime_put_sync(up->dev);
1671 pm_runtime_disable(up->dev);
1672 cpu_latency_qos_remove_request(&up->pm_qos_request);
1687 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1691 serial_out(up, UART_OMAP_MDR1, mdr1);
1693 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1699 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1704 dev_crit(up->dev, "Errata i202: timedout %x\n",
1705 serial_in(up, UART_LSR));
1713 static void serial_omap_restore_context(struct uart_omap_port *up)
1715 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1716 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1718 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1720 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1721 serial_out(up, UART_EFR, UART_EFR_ECB);
1722 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1723 serial_out(up, UART_IER, 0x0);
1724 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1725 serial_out(up, UART_DLL, up->dll);
1726 serial_out(up, UART_DLM, up->dlh);
1727 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1728 serial_out(up, UART_IER, up->ier);
1729 serial_out(up, UART_FCR, up->fcr);
1730 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1731 serial_out(up, UART_MCR, up->mcr);
1732 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1733 serial_out(up, UART_OMAP_SCR, up->scr);
1734 serial_out(up, UART_EFR, up->efr);
1735 serial_out(up, UART_LCR, up->lcr);
1736 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1737 serial_omap_mdr1_errataset(up, up->mdr1);
1739 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1740 serial_out(up, UART_OMAP_WER, up->wer);
1745 struct uart_omap_port *up = dev_get_drvdata(dev);
1747 if (!up)
1756 if (up->is_suspending && !console_suspend_enabled &&
1757 uart_console(&up->port))
1760 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1762 serial_omap_enable_wakeup(up, true);
1764 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1765 schedule_work(&up->qos_work);
1772 struct uart_omap_port *up = dev_get_drvdata(dev);
1774 int loss_cnt = serial_omap_get_context_loss_count(up);
1776 serial_omap_enable_wakeup(up, false);
1781 serial_omap_restore_context(up);
1782 } else if (up->context_loss_cnt != loss_cnt) {
1783 serial_omap_restore_context(up);
1785 up->latency = up->calc_latency;
1786 schedule_work(&up->qos_work);