Lines Matching refs:port
134 /* Driver data, a structure for each UART port */
154 struct uart_port *port;
163 static struct mvebu_uart *to_mvuart(struct uart_port *port)
165 return (struct mvebu_uart *)port->private_data;
168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
175 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
176 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
177 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
178 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
185 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
190 spin_lock_irqsave(&port->lock, flags);
191 st = readl(port->membase + UART_STAT);
192 spin_unlock_irqrestore(&port->lock, flags);
197 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
202 static void mvebu_uart_set_mctrl(struct uart_port *port,
211 static void mvebu_uart_stop_tx(struct uart_port *port)
213 unsigned int ctl = readl(port->membase + UART_INTR(port));
215 ctl &= ~CTRL_TX_RDY_INT(port);
216 writel(ctl, port->membase + UART_INTR(port));
219 static void mvebu_uart_start_tx(struct uart_port *port)
222 struct circ_buf *xmit = &port->state->xmit;
224 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
226 uart_xmit_advance(port, 1);
229 ctl = readl(port->membase + UART_INTR(port));
230 ctl |= CTRL_TX_RDY_INT(port);
231 writel(ctl, port->membase + UART_INTR(port));
234 static void mvebu_uart_stop_rx(struct uart_port *port)
238 ctl = readl(port->membase + UART_CTRL(port));
240 writel(ctl, port->membase + UART_CTRL(port));
242 ctl = readl(port->membase + UART_INTR(port));
243 ctl &= ~CTRL_RX_RDY_INT(port);
244 writel(ctl, port->membase + UART_INTR(port));
247 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
252 spin_lock_irqsave(&port->lock, flags);
253 ctl = readl(port->membase + UART_CTRL(port));
258 writel(ctl, port->membase + UART_CTRL(port));
259 spin_unlock_irqrestore(&port->lock, flags);
262 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
264 struct tty_port *tport = &port->state->port;
270 if (status & STAT_RX_RDY(port)) {
271 ch = readl(port->membase + UART_RBR(port));
274 port->icount.rx++;
277 port->icount.parity++;
284 if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) {
285 ret = readl(port->membase + UART_STAT);
287 writel(ret, port->membase + UART_STAT);
291 port->icount.brk++;
293 if (uart_handle_break(port))
298 port->icount.overrun++;
301 port->icount.frame++;
303 if (uart_handle_sysrq_char(port, ch))
306 if (status & port->ignore_status_mask & STAT_PAR_ERR)
307 status &= ~STAT_RX_RDY(port);
309 status &= port->read_status_mask;
314 status &= ~port->ignore_status_mask;
316 if (status & STAT_RX_RDY(port))
329 status = readl(port->membase + UART_STAT);
330 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
335 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
339 uart_port_tx_limited(port, ch, port->fifosize,
340 !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL),
341 writel(ch, port->membase + UART_TSH(port)),
347 struct uart_port *port = (struct uart_port *)dev_id;
348 unsigned int st = readl(port->membase + UART_STAT);
350 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
352 mvebu_uart_rx_chars(port, st);
354 if (st & STAT_TX_RDY(port))
355 mvebu_uart_tx_chars(port, st);
362 struct uart_port *port = (struct uart_port *)dev_id;
363 unsigned int st = readl(port->membase + UART_STAT);
365 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
367 mvebu_uart_rx_chars(port, st);
374 struct uart_port *port = (struct uart_port *)dev_id;
375 unsigned int st = readl(port->membase + UART_STAT);
377 if (st & STAT_TX_RDY(port))
378 mvebu_uart_tx_chars(port, st);
383 static int mvebu_uart_startup(struct uart_port *port)
385 struct mvebu_uart *mvuart = to_mvuart(port);
390 port->membase + UART_CTRL(port));
394 ret = readl(port->membase + UART_STAT);
396 writel(ret, port->membase + UART_STAT);
398 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
400 ctl = readl(port->membase + UART_INTR(port));
401 ctl |= CTRL_RX_RDY_INT(port);
402 writel(ctl, port->membase + UART_INTR(port));
406 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
407 mvebu_uart_isr, port->irqflags,
408 dev_name(port->dev), port);
410 dev_err(port->dev, "unable to request IRQ %d\n",
416 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
417 mvebu_uart_rx_isr, port->irqflags,
418 dev_name(port->dev), port);
420 dev_err(port->dev, "unable to request IRQ %d\n",
425 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
426 mvebu_uart_tx_isr, port->irqflags,
427 dev_name(port->dev),
428 port);
430 dev_err(port->dev, "unable to request IRQ %d\n",
432 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
433 port);
441 static void mvebu_uart_shutdown(struct uart_port *port)
443 struct mvebu_uart *mvuart = to_mvuart(port);
445 writel(0, port->membase + UART_INTR(port));
448 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
450 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
451 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
455 static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
461 if (!port->uartclk)
496 * Member port->uartclk is either xtal clock rate or TBG clock rate
503 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
511 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
520 brdv = readl(port->membase + UART_BRDV);
523 writel(brdv, port->membase + UART_BRDV);
526 osamp = readl(port->membase + UART_OSAMP);
531 writel(osamp, port->membase + UART_OSAMP);
533 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor);
536 static void mvebu_uart_set_termios(struct uart_port *port,
543 spin_lock_irqsave(&port->lock, flags);
545 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
546 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
549 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
551 port->ignore_status_mask = 0;
553 port->ignore_status_mask |=
557 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
563 * rate. If port->uartclk is not available, then
567 min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX *
569 max_baud = port->uartclk / 80;
571 baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
572 baud = mvebu_uart_baud_rate_set(port, baud);
589 uart_update_timeout(port, termios->c_cflag, baud);
592 spin_unlock_irqrestore(&port->lock, flags);
595 static const char *mvebu_uart_type(struct uart_port *port)
600 static void mvebu_uart_release_port(struct uart_port *port)
605 static int mvebu_uart_request_port(struct uart_port *port)
611 static int mvebu_uart_get_poll_char(struct uart_port *port)
613 unsigned int st = readl(port->membase + UART_STAT);
615 if (!(st & STAT_RX_RDY(port)))
618 return readl(port->membase + UART_RBR(port));
621 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
626 st = readl(port->membase + UART_STAT);
634 writel(c, port->membase + UART_TSH(port));
662 static void mvebu_uart_putc(struct uart_port *port, unsigned char c)
667 st = readl(port->membase + UART_STAT);
673 writel(c, port->membase + UART_STD_TSH);
676 st = readl(port->membase + UART_STAT);
688 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
695 if (!device->port.membase)
707 static void wait_for_xmitr(struct uart_port *port)
711 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
712 (val & STAT_TX_RDY(port)), 1, 10000);
715 static void wait_for_xmite(struct uart_port *port)
719 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
723 static void mvebu_uart_console_putchar(struct uart_port *port, unsigned char ch)
725 wait_for_xmitr(port);
726 writel(ch, port->membase + UART_TSH(port));
732 struct uart_port *port = &mvebu_uart_ports[co->index];
738 locked = spin_trylock_irqsave(&port->lock, flags);
740 spin_lock_irqsave(&port->lock, flags);
742 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
743 intr = readl(port->membase + UART_INTR(port)) &
744 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
745 writel(0, port->membase + UART_CTRL(port));
746 writel(0, port->membase + UART_INTR(port));
748 uart_console_write(port, s, count, mvebu_uart_console_putchar);
750 wait_for_xmite(port);
753 writel(ier, port->membase + UART_CTRL(port));
756 ctl = intr | readl(port->membase + UART_INTR(port));
757 writel(ctl, port->membase + UART_INTR(port));
761 spin_unlock_irqrestore(&port->lock, flags);
766 struct uart_port *port;
775 port = &mvebu_uart_ports[co->index];
777 if (!port->mapbase || !port->membase) {
785 return uart_set_options(port, co, baud, parity, bits, flow);
825 struct uart_port *port = mvuart->port;
828 uart_suspend_port(&mvebu_uart_driver, port);
830 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
831 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
832 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
833 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
834 mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
836 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
838 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
848 struct uart_port *port = mvuart->port;
851 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
852 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
853 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
854 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
855 writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
857 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
859 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
861 uart_resume_port(&mvebu_uart_driver, port);
874 /* Counter to keep track of each UART port id when not using CONFIG_OF */
881 struct uart_port *port;
899 port = &mvebu_uart_ports[pdev->id];
901 spin_lock_init(&port->lock);
903 port->dev = &pdev->dev;
904 port->type = PORT_MVEBU;
905 port->ops = &mvebu_uart_ops;
906 port->regshift = 0;
908 port->fifosize = 32;
909 port->iotype = UPIO_MEM32;
910 port->flags = UPF_FIXED_PORT;
911 port->line = pdev->id;
915 * them per port (RX and TX). Instead, use the driver UART structure
918 port->irq = 0;
919 port->irqflags = 0;
921 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, ®);
922 if (IS_ERR(port->membase))
923 return PTR_ERR(port->membase);
924 port->mapbase = reg->start;
933 mvuart->port = port;
935 port->private_data = mvuart;
944 if (IS_EXTENDED(port)) {
950 port->uartclk = clk_get_rate(mvuart->clk);
965 * uart-sum of UART0 port.
981 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
983 writel(0, port->membase + UART_CTRL(port));
985 return uart_add_one_port(&mvebu_uart_driver, port);