Lines Matching refs:membase

191 	st = readl(port->membase + UART_STAT);
213 	unsigned int ctl = readl(port->membase + UART_INTR(port));
216 	writel(ctl, port->membase + UART_INTR(port));
225 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
229 	ctl = readl(port->membase + UART_INTR(port));
231 	writel(ctl, port->membase + UART_INTR(port));
238 	ctl = readl(port->membase + UART_CTRL(port));
240 	writel(ctl, port->membase + UART_CTRL(port));
242 	ctl = readl(port->membase + UART_INTR(port));
244 	writel(ctl, port->membase + UART_INTR(port));
253 	ctl = readl(port->membase + UART_CTRL(port));
258 	writel(ctl, port->membase + UART_CTRL(port));
271 			ch = readl(port->membase + UART_RBR(port));
285 			ret = readl(port->membase + UART_STAT);
287 			writel(ret, port->membase + UART_STAT);
329 		status = readl(port->membase + UART_STAT);
340 		!(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL),
341 		writel(ch, port->membase + UART_TSH(port)),
348 	unsigned int st = readl(port->membase + UART_STAT);
363 	unsigned int st = readl(port->membase + UART_STAT);
375 	unsigned int st = readl(port->membase + UART_STAT);
390 	       port->membase + UART_CTRL(port));
394 	ret = readl(port->membase + UART_STAT);
396 	writel(ret, port->membase + UART_STAT);
398 	writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
400 	ctl = readl(port->membase + UART_INTR(port));
402 	writel(ctl, port->membase + UART_INTR(port));
445 	writel(0, port->membase + UART_INTR(port));
520 	brdv = readl(port->membase + UART_BRDV);
523 	writel(brdv, port->membase + UART_BRDV);
526 	osamp = readl(port->membase + UART_OSAMP);
531 	writel(osamp, port->membase + UART_OSAMP);
613 	unsigned int st = readl(port->membase + UART_STAT);
618 	return readl(port->membase + UART_RBR(port));
626 		st = readl(port->membase + UART_STAT);
634 	writel(c, port->membase + UART_TSH(port));
667 		st = readl(port->membase + UART_STAT);
673 	writel(c, port->membase + UART_STD_TSH);
676 		st = readl(port->membase + UART_STAT);
695 	if (!device->port.membase)
711 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
719 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
726 	writel(ch, port->membase + UART_TSH(port));
742 	ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
743 	intr = readl(port->membase + UART_INTR(port)) &
745 	writel(0, port->membase + UART_CTRL(port));
746 	writel(0, port->membase + UART_INTR(port));
753 		writel(ier, port->membase + UART_CTRL(port));
756 		ctl = intr | readl(port->membase + UART_INTR(port));
757 		writel(ctl, port->membase + UART_INTR(port));
777 	if (!port->mapbase || !port->membase) {
830 	mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
831 	mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
832 	mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
833 	mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
834 	mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
836 	mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
838 	mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
851 	writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
852 	writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
853 	writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
854 	writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
855 	writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
857 	writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
859 	writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
921 	port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &reg);
922 	if (IS_ERR(port->membase))
923 		return PTR_ERR(port->membase);
981 	writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
983 	writel(0, port->membase + UART_CTRL(port));