Lines Matching defs:uart_clock_base
1065 struct mvebu_uart_clock_base *uart_clock_base =
1091 if (uart_clock_base->configured) {
1096 parent_clock_idx = uart_clock_base->parent_idx;
1097 parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx];
1099 val = readl(uart_clock_base->reg1);
1101 if (uart_clock_base->div > CLK_TBG_DIV1_MAX) {
1103 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX;
1105 d1 = uart_clock_base->div;
1118 /* Note that uart_clock_base->parent_rates[i] may not be available */
1119 prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx];
1147 writel(val, uart_clock_base->reg1);
1151 val = readl(uart_clock_base->reg2);
1160 writel(val, uart_clock_base->reg2);
1163 uart_clock_base->configured = true;
1173 struct mvebu_uart_clock_base *uart_clock_base =
1180 val = readl(uart_clock_base->reg1);
1187 writel(val, uart_clock_base->reg1);
1197 struct mvebu_uart_clock_base *uart_clock_base =
1204 val = readl(uart_clock_base->reg1);
1211 writel(val, uart_clock_base->reg1);
1219 struct mvebu_uart_clock_base *uart_clock_base =
1223 val = readl(uart_clock_base->reg1);
1234 struct mvebu_uart_clock_base *uart_clock_base =
1239 uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1);
1240 uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2);
1249 struct mvebu_uart_clock_base *uart_clock_base =
1254 writel(uart_clock->pm_context_reg1, uart_clock_base->reg1);
1255 writel(uart_clock->pm_context_reg2, uart_clock_base->reg2);
1263 struct mvebu_uart_clock_base *uart_clock_base =
1266 return parent_rate / uart_clock_base->div;
1273 struct mvebu_uart_clock_base *uart_clock_base =
1276 return *parent_rate / uart_clock_base->div;
1328 struct mvebu_uart_clock_base *uart_clock_base;
1337 ARRAY_SIZE(uart_clock_base->clocks));
1339 ARRAY_SIZE(uart_clock_base->parent_rates));
1341 uart_clock_base = devm_kzalloc(dev,
1342 sizeof(*uart_clock_base),
1344 if (!uart_clock_base)
1361 uart_clock_base->reg1 = devm_ioremap(dev, res->start,
1363 if (!uart_clock_base->reg1)
1380 uart_clock_base->reg2 = devm_ioremap(dev, res->start,
1382 if (!uart_clock_base->reg2)
1394 hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw;
1395 uart_clock_base->clocks[i].clock_idx = i;
1417 uart_clock_base->parent_rates[i] = rate;
1473 uart_clock_base->parent_idx = parent_clk_idx;
1474 uart_clock_base->div = div;
1481 &uart_clock_base->clocks[i],