Lines Matching defs:rate
496 * Member port->uartclk is either xtal clock rate or TBG clock rate
561 * experiments show that baudrates above 1/80 of parent clock rate are
563 * rate. If port->uartclk is not available, then
1269 static long mvebu_uart_clock_round_rate(struct clk_hw *hw, unsigned long rate,
1279 static int mvebu_uart_clock_set_rate(struct clk_hw *hw, unsigned long rate,
1332 unsigned long div, rate;
1416 rate = clk_get_rate(parent_clks[i]);
1417 uart_clock_base->parent_rates[i] = rate;
1424 d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR *
1431 d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR *
1446 if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2)