Lines Matching defs:msm_write
190 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
206 msm_write(port, 0x06, MSM_UART_MREG);
207 msm_write(port, 0xF1, MSM_UART_NREG);
208 msm_write(port, 0x0F, MSM_UART_DREG);
209 msm_write(port, 0x1A, MSM_UART_MNDREG);
218 msm_write(port, 0x18, MSM_UART_MREG);
219 msm_write(port, 0xF6, MSM_UART_NREG);
220 msm_write(port, 0x0F, MSM_UART_DREG);
221 msm_write(port, 0x0A, MSM_UART_MNDREG);
265 msm_write(port, val, UARTDM_DMEN);
405 msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);
413 msm_write(port, msm_port->imr, MSM_UART_IMR);
426 msm_write(port, msm_port->imr, MSM_UART_IMR);
432 msm_write(port, count, UARTDM_NCF_TX);
459 msm_write(port, val, UARTDM_DMEN);
462 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
463 msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);
472 msm_write(port, msm_port->imr, MSM_UART_IMR);
520 msm_write(port, msm_port->imr, MSM_UART_IMR);
528 msm_write(port, val, UARTDM_DMEN);
533 msm_write(port, val, UARTDM_DMEN);
560 msm_write(port, val, UARTDM_DMEN);
565 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
650 msm_write(uart, msm_port->imr, MSM_UART_IMR);
656 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
657 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
663 msm_write(uart, val, UARTDM_DMEN);
665 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
668 msm_write(uart, val, UARTDM_DMEN);
679 msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
680 msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
682 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
683 msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
684 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
688 msm_write(uart, msm_port->imr, MSM_UART_IMR);
697 msm_write(port, msm_port->imr, MSM_UART_IMR);
708 msm_write(port, msm_port->imr, MSM_UART_IMR);
722 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
777 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
778 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
779 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
798 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
940 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
956 msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */
960 msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);
966 msm_write(port, val, MSM_UART_CR);
968 msm_write(port, val, MSM_UART_CR);
985 msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */
1007 msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
1008 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
1009 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
1010 msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);
1011 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
1012 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1015 msm_write(port, mr, MSM_UART_MR1);
1019 msm_write(port, 0, UARTDM_DMEN);
1030 msm_write(port, mr, MSM_UART_MR1);
1031 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1034 msm_write(port, mr, MSM_UART_MR1);
1041 msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);
1043 msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);
1141 msm_write(port, entry->code, MSM_UART_CSR);
1155 msm_write(port, watermark, MSM_UART_IPR);
1159 msm_write(port, watermark, MSM_UART_RFWR);
1162 msm_write(port, 10, MSM_UART_TFWR);
1164 msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);
1168 msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
1174 msm_write(port, msm_port->imr, MSM_UART_IMR);
1177 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1178 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1179 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1222 msm_write(port, data, MSM_UART_MR1);
1251 msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */
1318 msm_write(port, mr, MSM_UART_MR2);
1327 msm_write(port, mr, MSM_UART_MR1);
1466 msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);
1470 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1471 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1472 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1494 msm_write(port, 0, MSM_UART_IMR);
1502 msm_write(port, imr, MSM_UART_IMR);
1514 msm_write(port, 0, MSM_UART_IMR);
1524 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF);
1531 msm_write(port, imr, MSM_UART_IMR);