Lines Matching defs:PSC
3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
75 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
83 /* PSC fifo operations for isolating differences between 52xx and 512x */
135 return in_be16(&PSC(port)->mpc52xx_psc_status);
140 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
145 out_8(&PSC(port)->command, cmd);
150 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
151 out_8(&PSC(port)->mode, mr1);
152 out_8(&PSC(port)->mode, mr2);
158 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
160 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
165 struct mpc52xx_psc __iomem *psc = PSC(port);
178 out_be32(&PSC(port)->sicr, val);
183 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
188 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
189 return in_8(&PSC(port)->mode);
193 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
196 struct mpc52xx_psc __iomem *psc = PSC(port);
210 return in_be16(&PSC(port)->mpc52xx_psc_status)
216 return in_be16(&PSC(port)->mpc52xx_psc_status)
223 return in_be16(&PSC(port)->mpc52xx_psc_isr)
230 return in_be16(&PSC(port)->mpc52xx_psc_isr)
237 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
245 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
251 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
257 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
270 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
275 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
280 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
285 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
302 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
328 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
407 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
409 /* PSC FIFO Controller for mpc512x */
425 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
550 * Chapter 4.1 PSC in UART Mode.
561 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
565 /* Init PSC FIFO Controller */
643 /* Read pending PSC FIFOC interrupts */
738 dev_err(port->dev, "Failed to get PSC clock entry!\n");
904 * MPC5125 have compatible PSC FIFO Controller.
1263 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1583 pr_debug("PSC%x out of range\n", co->index);
1588 pr_debug("PSC%x not found in device tree\n", co->index);
1598 pr_debug("Could not get resources for PSC%x\n", co->index);
1746 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1808 /* Find the first free PSC number */
1829 /* Assign index to each PSC in device tree */
1870 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1882 * Map the PSC FIFO Controller and init if on MPC512x.
1921 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");