Lines Matching refs:port
65 static void mlb_usio_stop_tx(struct uart_port *port)
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
68 port->membase + MLB_USIO_REG_FCR);
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
70 port->membase + MLB_USIO_REG_SCR);
73 static void mlb_usio_tx_chars(struct uart_port *port)
75 struct circ_buf *xmit = &port->state->xmit;
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
79 port->membase + MLB_USIO_REG_FCR);
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) &
82 port->membase + MLB_USIO_REG_SCR);
84 if (port->x_char) {
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR);
86 port->icount.tx++;
87 port->x_char = 0;
90 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
91 mlb_usio_stop_tx(port);
95 count = port->fifosize -
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
99 writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
101 uart_xmit_advance(port, 1);
107 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
108 port->membase + MLB_USIO_REG_FCR);
110 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
111 port->membase + MLB_USIO_REG_SCR);
114 uart_write_wakeup(port);
117 mlb_usio_stop_tx(port);
120 static void mlb_usio_start_tx(struct uart_port *port)
122 u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
124 writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
128 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
129 port->membase + MLB_USIO_REG_SCR);
131 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
132 mlb_usio_tx_chars(port);
135 static void mlb_usio_stop_rx(struct uart_port *port)
137 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
138 port->membase + MLB_USIO_REG_SCR);
141 static void mlb_usio_enable_ms(struct uart_port *port)
143 writeb(readb(port->membase + MLB_USIO_REG_SCR) |
145 port->membase + MLB_USIO_REG_SCR);
148 static void mlb_usio_rx_chars(struct uart_port *port)
150 struct tty_port *ttyport = &port->state->port;
156 status = readb(port->membase + MLB_USIO_REG_SSR);
163 ch = readw(port->membase + MLB_USIO_REG_DR);
165 port->icount.rx++;
166 if (uart_handle_sysrq_char(port, ch))
168 uart_insert_char(port, status, MLB_USIO_SSR_ORE,
173 port->icount.parity++;
175 port->icount.overrun++;
176 status &= port->read_status_mask;
190 uart_insert_char(port, status, MLB_USIO_SSR_ORE,
193 writeb(readb(port->membase + MLB_USIO_REG_SSR) |
195 port->membase + MLB_USIO_REG_SSR);
197 max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
198 writew(readw(port->membase + MLB_USIO_REG_FCR) |
200 port->membase + MLB_USIO_REG_FCR);
208 struct uart_port *port = dev_id;
210 spin_lock(&port->lock);
211 mlb_usio_rx_chars(port);
212 spin_unlock(&port->lock);
219 struct uart_port *port = dev_id;
221 spin_lock(&port->lock);
222 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
223 mlb_usio_tx_chars(port);
224 spin_unlock(&port->lock);
229 static unsigned int mlb_usio_tx_empty(struct uart_port *port)
231 return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
235 static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
239 static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
245 static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
249 static int mlb_usio_startup(struct uart_port *port)
251 const char *portname = to_platform_device(port->dev)->name;
253 int ret, index = port->line;
257 0, portname, port);
261 0, portname, port);
263 free_irq(mlb_usio_irq[index][RX], port);
267 escr = readb(port->membase + MLB_USIO_REG_ESCR);
268 if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
270 spin_lock_irqsave(&port->lock, flags);
271 writeb(0, port->membase + MLB_USIO_REG_SCR);
272 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
273 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
274 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
275 writew(0, port->membase + MLB_USIO_REG_FCR);
277 port->membase + MLB_USIO_REG_FCR);
279 port->membase + MLB_USIO_REG_FCR);
280 writew(0, port->membase + MLB_USIO_REG_FBYTE);
281 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
284 MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
285 spin_unlock_irqrestore(&port->lock, flags);
290 static void mlb_usio_shutdown(struct uart_port *port)
292 int index = port->line;
294 free_irq(mlb_usio_irq[index][RX], port);
295 free_irq(mlb_usio_irq[index][TX], port);
298 static void mlb_usio_set_termios(struct uart_port *port,
330 if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
334 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
336 quot = port->uartclk / baud - 1;
340 spin_lock_irqsave(&port->lock, flags);
341 uart_update_timeout(port, termios->c_cflag, baud);
342 port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
345 port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
347 port->ignore_status_mask = 0;
349 port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
351 port->ignore_status_mask |= MLB_USIO_SSR_ORE;
353 port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
355 writeb(0, port->membase + MLB_USIO_REG_SCR);
356 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
357 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
358 writew(0, port->membase + MLB_USIO_REG_FCR);
359 writeb(smr, port->membase + MLB_USIO_REG_SMR);
360 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
361 writew(quot, port->membase + MLB_USIO_REG_BGR);
362 writew(0, port->membase + MLB_USIO_REG_FCR);
365 port->membase + MLB_USIO_REG_FCR);
366 writew(0, port->membase + MLB_USIO_REG_FBYTE);
367 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
369 MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
370 spin_unlock_irqrestore(&port->lock, flags);
373 static const char *mlb_usio_type(struct uart_port *port)
375 return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
378 static void mlb_usio_config_port(struct uart_port *port, int flags)
381 port->type = PORT_MLB_USIO;
402 static void mlb_usio_console_putchar(struct uart_port *port, unsigned char c)
404 while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
407 writew(c, port->membase + MLB_USIO_REG_DR);
413 struct uart_port *port = &mlb_usio_ports[co->index];
415 uart_console_write(port, s, count, mlb_usio_console_putchar);
420 struct uart_port *port;
429 port = &mlb_usio_ports[co->index];
430 if (!port->membase)
437 if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
440 return uart_set_options(port, co, baud, parity, bits, flow);
468 uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
474 if (!device->port.membase)
499 struct uart_port *port;
514 port = &mlb_usio_ports[index];
516 port->private_data = (void *)clk;
523 port->membase = devm_ioremap(&pdev->dev, res->start,
532 port->irq = mlb_usio_irq[index][RX];
533 port->uartclk = clk_get_rate(clk);
534 port->fifosize = 128;
535 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE);
536 port->iotype = UPIO_MEM32;
537 port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
538 port->line = index;
539 port->ops = &mlb_usio_ops;
540 port->dev = &pdev->dev;
542 ret = uart_add_one_port(&mlb_usio_uart_driver, port);
544 dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
557 struct uart_port *port = &mlb_usio_ports[pdev->id];
558 struct clk *clk = port->private_data;
560 uart_remove_one_port(&mlb_usio_uart_driver, port);