Lines Matching refs:membase
102 val = readl(port->membase + AML_UART_STATUS);
111 val = readl(port->membase + AML_UART_CONTROL);
113 writel(val, port->membase + AML_UART_CONTROL);
120 val = readl(port->membase + AML_UART_CONTROL);
122 writel(val, port->membase + AML_UART_CONTROL);
134 val = readl(port->membase + AML_UART_CONTROL);
137 writel(val, port->membase + AML_UART_CONTROL);
153 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
155 writel(port->x_char, port->membase + AML_UART_WFIFO);
165 writel(ch, port->membase + AML_UART_WFIFO);
170 val = readl(port->membase + AML_UART_CONTROL);
172 writel(val, port->membase + AML_UART_CONTROL);
188 ostatus = status = readl(port->membase + AML_UART_STATUS);
198 mode = readl(port->membase + AML_UART_CONTROL);
200 writel(mode, port->membase + AML_UART_CONTROL);
204 writel(mode, port->membase + AML_UART_CONTROL);
213 ch = readl(port->membase + AML_UART_RFIFO);
232 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
246 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
247 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
273 val = readl(port->membase + AML_UART_CONTROL);
275 writel(val, port->membase + AML_UART_CONTROL);
278 writel(val, port->membase + AML_UART_CONTROL);
289 val = readl(port->membase + AML_UART_CONTROL);
291 writel(val, port->membase + AML_UART_CONTROL);
293 writel(val, port->membase + AML_UART_CONTROL);
296 writel(val, port->membase + AML_UART_CONTROL);
299 writel(val, port->membase + AML_UART_CONTROL);
302 writel(val, port->membase + AML_UART_MISC);
333 writel(val, port->membase + AML_UART_REG5);
349 val = readl(port->membase + AML_UART_CONTROL);
392 writel(val, port->membase + AML_UART_CONTROL);
427 devm_iounmap(port->dev, port->membase);
428 port->membase = NULL;
440 port->membase = devm_ioremap(port->dev, port->mapbase,
442 if (!port->membase)
469 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
472 c = readl(port->membase + AML_UART_RFIFO);
488 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
498 writel(c, port->membase + AML_UART_WFIFO);
501 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
540 val = readl(port->membase + AML_UART_CONTROL);
542 writel(val, port->membase + AML_UART_CONTROL);
547 if (!port->membase)
550 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
552 writel(ch, port->membase + AML_UART_WFIFO);
572 val = readl(port->membase + AML_UART_CONTROL);
574 writel(tmp, port->membase + AML_UART_CONTROL);
577 writel(val, port->membase + AML_UART_CONTROL);
608 if (!port || !port->membase)
645 if (!device->port.membase)