Lines Matching refs:writeb
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
109 writeb(pp->imr, port->membase + MCFUART_UIMR);
119 writeb(pp->imr, port->membase + MCFUART_UIMR);
129 writeb(pp->imr, port->membase + MCFUART_UIMR);
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
142 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
156 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
157 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
160 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
165 writeb(pp->imr, port->membase + MCFUART_UIMR);
183 writeb(pp->imr, port->membase + MCFUART_UIMR);
186 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
187 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
262 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
263 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
264 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
265 writeb(mr1, port->membase + MCFUART_UMR);
266 writeb(mr2, port->membase + MCFUART_UMR);
267 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
268 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
270 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
272 writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
274 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
292 writeb(MCFUART_UCR_CMDRESETERR,
335 writeb(ch, port->membase + MCFUART_UTB));
339 writeb(MCFUART_UCR_TXDISABLE, port->membase + MCFUART_UCR);
375 writeb(0, port->membase + MCFUART_UIMR);
432 writeb(mr1, port->membase + MCFUART_UMR);
433 writeb(mr2, port->membase + MCFUART_UMR);
509 writeb(c, port->membase + MCFUART_UTB);