Lines Matching defs:linestatus
278 u8 linestatus = 0;
290 linestatus = ch->ch_cached_lsr;
331 * Grab the linestatus register, we need to check
334 linestatus = readb(&ch->ch_neo_uart->lsr);
341 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
356 * Since we are grabbing the linestatus register, which
360 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
363 linestatus = 0;
395 * Its possible we have a linestatus from the loop above
398 linestatus |= readb(&ch->ch_neo_uart->lsr);
403 * But before we do, cache the linestatus, just in case.
405 if (!(linestatus & UART_LSR_DR)) {
406 ch->ch_cached_lsr = linestatus;
411 linestatus &= ~UART_LSR_DR;
414 * Since we are grabbing the linestatus register, which
418 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
419 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
426 if (linestatus & error_mask) {
428 linestatus = 0;
452 ch->ch_equeue[head] = (u8) linestatus;
457 /* Ditch any remaining linestatus value. */
458 linestatus = 0;
828 int linestatus;
841 linestatus = readb(&ch->ch_neo_uart->lsr);
843 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
844 __FILE__, __LINE__, port, linestatus);
846 ch->ch_cached_lsr |= linestatus;
862 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
872 if (linestatus & UART_LSR_PE) {
878 if (linestatus & UART_LSR_FE) {
884 if (linestatus & UART_LSR_BI) {
891 if (linestatus & UART_LSR_OE) {
904 if (linestatus & UART_LSR_THRE) {
912 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {