Lines Matching refs:ch
52 static void cls_set_cts_flow_control(struct jsm_channel *ch)
54 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
55 u8 ier = readb(&ch->ch_cls_uart->ier);
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
73 writeb(lcrb, &ch->ch_cls_uart->lcr);
81 writeb(ier, &ch->ch_cls_uart->ier);
84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
88 &ch->ch_cls_uart->isr_fcr);
90 ch->ch_t_tlevel = 16;
93 static void cls_set_ixon_flow_control(struct jsm_channel *ch)
95 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
96 u8 ier = readb(&ch->ch_cls_uart->ier);
103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
105 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
115 writeb(0, &ch->ch_cls_uart->lsr);
116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
117 writeb(0, &ch->ch_cls_uart->spr);
120 writeb(lcrb, &ch->ch_cls_uart->lcr);
128 writeb(ier, &ch->ch_cls_uart->ier);
131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
135 &ch->ch_cls_uart->isr_fcr);
138 static void cls_set_no_output_flow_control(struct jsm_channel *ch)
140 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
141 u8 ier = readb(&ch->ch_cls_uart->ier);
148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
150 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
159 writeb(lcrb, &ch->ch_cls_uart->lcr);
167 writeb(ier, &ch->ch_cls_uart->ier);
170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
174 &ch->ch_cls_uart->isr_fcr);
176 ch->ch_r_watermark = 0;
177 ch->ch_t_tlevel = 16;
178 ch->ch_r_tlevel = 16;
181 static void cls_set_rts_flow_control(struct jsm_channel *ch)
183 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
184 u8 ier = readb(&ch->ch_cls_uart->ier);
191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
193 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
202 writeb(lcrb, &ch->ch_cls_uart->lcr);
206 writeb(ier, &ch->ch_cls_uart->ier);
209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
213 &ch->ch_cls_uart->isr_fcr);
215 ch->ch_r_watermark = 4;
216 ch->ch_r_tlevel = 8;
219 static void cls_set_ixoff_flow_control(struct jsm_channel *ch)
221 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
222 u8 ier = readb(&ch->ch_cls_uart->ier);
229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
231 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
241 writeb(0, &ch->ch_cls_uart->lsr);
242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
243 writeb(0, &ch->ch_cls_uart->spr);
246 writeb(lcrb, &ch->ch_cls_uart->lcr);
250 writeb(ier, &ch->ch_cls_uart->ier);
253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
257 &ch->ch_cls_uart->isr_fcr);
260 static void cls_set_no_input_flow_control(struct jsm_channel *ch)
262 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
263 u8 ier = readb(&ch->ch_cls_uart->ier);
270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
272 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
281 writeb(lcrb, &ch->ch_cls_uart->lcr);
285 writeb(ier, &ch->ch_cls_uart->ier);
288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
292 &ch->ch_cls_uart->isr_fcr);
294 ch->ch_t_tlevel = 16;
295 ch->ch_r_tlevel = 16;
305 static void cls_clear_break(struct jsm_channel *ch)
309 spin_lock_irqsave(&ch->ch_lock, lock_flags);
312 if (ch->ch_flags & CH_BREAK_SENDING) {
313 u8 temp = readb(&ch->ch_cls_uart->lcr);
315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
317 ch->ch_flags &= ~(CH_BREAK_SENDING);
318 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
322 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
325 static void cls_disable_receiver(struct jsm_channel *ch)
327 u8 tmp = readb(&ch->ch_cls_uart->ier);
330 writeb(tmp, &ch->ch_cls_uart->ier);
333 static void cls_enable_receiver(struct jsm_channel *ch)
335 u8 tmp = readb(&ch->ch_cls_uart->ier);
338 writeb(tmp, &ch->ch_cls_uart->ier);
342 static void cls_assert_modem_signals(struct jsm_channel *ch)
344 if (!ch)
347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr);
350 static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch)
359 if (!ch)
362 spin_lock_irqsave(&ch->ch_lock, flags);
365 head = ch->ch_r_head & RQUEUEMASK;
366 tail = ch->ch_r_tail & RQUEUEMASK;
368 ch->ch_cached_lsr = 0;
379 if (ch->ch_c_iflag & IGNBRK)
387 linestatus = readb(&ch->ch_cls_uart->lsr);
399 readb(&ch->ch_cls_uart->txrx);
413 ch->ch_r_tail = tail;
414 ch->ch_err_overrun++;
418 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
420 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
424 if (ch->ch_equeue[head] & UART_LSR_PE)
425 ch->ch_err_parity++;
426 if (ch->ch_equeue[head] & UART_LSR_BI)
427 ch->ch_err_break++;
428 if (ch->ch_equeue[head] & UART_LSR_FE)
429 ch->ch_err_frame++;
433 ch->ch_rxcount++;
439 ch->ch_r_head = head & RQUEUEMASK;
440 ch->ch_e_head = head & EQUEUEMASK;
442 spin_unlock_irqrestore(&ch->ch_lock, flags);
445 static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch)
453 if (!ch)
456 circ = &ch->uart_port.state->xmit;
463 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
467 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
480 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx);
483 ch->ch_txcount++;
490 if (len_written > ch->ch_t_tlevel)
491 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
494 uart_write_wakeup(&ch->uart_port);
497 static void cls_parse_modem(struct jsm_channel *ch, u8 signals)
501 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
503 ch->ch_portnum, msignals);
513 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
515 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS);
518 ch->ch_mistat |= UART_MSR_DCD;
520 ch->ch_mistat &= ~UART_MSR_DCD;
523 ch->ch_mistat |= UART_MSR_DSR;
525 ch->ch_mistat &= ~UART_MSR_DSR;
528 ch->ch_mistat |= UART_MSR_RI;
530 ch->ch_mistat &= ~UART_MSR_RI;
533 ch->ch_mistat |= UART_MSR_CTS;
535 ch->ch_mistat &= ~UART_MSR_CTS;
537 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
539 ch->ch_portnum,
540 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
541 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
542 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
543 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
544 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
545 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
551 struct jsm_channel *ch;
563 ch = brd->channels[port];
564 if (!ch)
569 isr = readb(&ch->ch_cls_uart->isr_fcr);
578 cls_copy_data_from_uart_to_queue(ch);
579 jsm_check_queue_flow_control(ch);
585 spin_lock_irqsave(&ch->ch_lock, flags);
586 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
587 spin_unlock_irqrestore(&ch->ch_lock, flags);
588 cls_copy_data_from_queue_to_uart(ch);
598 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
603 static void cls_flush_uart_write(struct jsm_channel *ch)
608 if (!ch)
612 &ch->ch_cls_uart->isr_fcr);
616 tmp = readb(&ch->ch_cls_uart->isr_fcr);
618 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
625 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
629 static void cls_flush_uart_read(struct jsm_channel *ch)
631 if (!ch)
648 static void cls_send_start_character(struct jsm_channel *ch)
650 if (!ch)
653 if (ch->ch_startc != __DISABLED_CHAR) {
654 ch->ch_xon_sends++;
655 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
659 static void cls_send_stop_character(struct jsm_channel *ch)
661 if (!ch)
664 if (ch->ch_stopc != __DISABLED_CHAR) {
665 ch->ch_xoff_sends++;
666 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
674 static void cls_param(struct jsm_channel *ch)
685 bd = ch->ch_bd;
692 if ((ch->ch_c_cflag & CBAUD) == B0) {
693 ch->ch_r_head = 0;
694 ch->ch_r_tail = 0;
695 ch->ch_e_head = 0;
696 ch->ch_e_tail = 0;
698 cls_flush_uart_write(ch);
699 cls_flush_uart_read(ch);
702 ch->ch_flags |= (CH_BAUD0);
703 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
704 cls_assert_modem_signals(ch);
708 cflag = C_BAUD(ch->uart_port.state->port.tty);
717 if (ch->ch_flags & CH_BAUD0)
718 ch->ch_flags &= ~(CH_BAUD0);
720 if (ch->ch_c_cflag & PARENB)
723 if (!(ch->ch_c_cflag & PARODD))
726 if (ch->ch_c_cflag & CMSPAR)
729 if (ch->ch_c_cflag & CSTOPB)
732 lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));
734 ier = readb(&ch->ch_cls_uart->ier);
735 uart_lcr = readb(&ch->ch_cls_uart->lcr);
737 quot = ch->ch_bd->bd_dividend / baud;
740 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
741 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
742 writeb((quot >> 8), &ch->ch_cls_uart->ier);
743 writeb(lcr, &ch->ch_cls_uart->lcr);
747 writeb(lcr, &ch->ch_cls_uart->lcr);
749 if (ch->ch_c_cflag & CREAD)
754 writeb(ier, &ch->ch_cls_uart->ier);
756 if (ch->ch_c_cflag & CRTSCTS)
757 cls_set_cts_flow_control(ch);
758 else if (ch->ch_c_iflag & IXON) {
763 if ((ch->ch_startc == __DISABLED_CHAR) ||
764 (ch->ch_stopc == __DISABLED_CHAR))
765 cls_set_no_output_flow_control(ch);
767 cls_set_ixon_flow_control(ch);
769 cls_set_no_output_flow_control(ch);
771 if (ch->ch_c_cflag & CRTSCTS)
772 cls_set_rts_flow_control(ch);
773 else if (ch->ch_c_iflag & IXOFF) {
778 if ((ch->ch_startc == __DISABLED_CHAR) ||
779 (ch->ch_stopc == __DISABLED_CHAR))
780 cls_set_no_input_flow_control(ch);
782 cls_set_ixoff_flow_control(ch);
784 cls_set_no_input_flow_control(ch);
786 cls_assert_modem_signals(ch);
789 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
835 static void cls_uart_init(struct jsm_channel *ch)
837 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
840 writeb(0, &ch->ch_cls_uart->ier);
846 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
848 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
853 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
856 writeb(lcrb, &ch->ch_cls_uart->lcr);
859 readb(&ch->ch_cls_uart->txrx);
862 &ch->ch_cls_uart->isr_fcr);
865 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
867 readb(&ch->ch_cls_uart->lsr);
868 readb(&ch->ch_cls_uart->msr);
874 static void cls_uart_off(struct jsm_channel *ch)
877 writeb(0, &ch->ch_cls_uart->ier);
886 static u32 cls_get_uart_bytes_left(struct jsm_channel *ch)
889 u8 lsr = readb(&ch->ch_cls_uart->lsr);
895 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
908 static void cls_send_break(struct jsm_channel *ch)
911 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
912 u8 temp = readb(&ch->ch_cls_uart->lcr);
914 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
915 ch->ch_flags |= (CH_BREAK_SENDING);
926 static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c)
928 writeb(c, &ch->ch_cls_uart->txrx);