Lines Matching refs:up
233 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
236 if (!ZS_REGS_HELD(up)) {
237 if (ZS_TX_ACTIVE(up)) {
238 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
240 __load_zsregs(channel, up->curregs);
248 static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
253 bool push = up->port.state != NULL;
271 ch &= up->parity_mask;
275 r1 |= up->tty_break;
279 up->port.icount.rx++;
281 up->tty_break = 0;
284 up->port.icount.brk++;
290 up->port.icount.parity++;
292 up->port.icount.frame++;
294 up->port.icount.overrun++;
295 r1 &= up->port.read_status_mask;
304 if (uart_handle_sysrq_char(&up->port, ch))
308 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
313 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
325 if (up->curregs[R15] & BRKIE) {
326 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
327 if (uart_handle_break(&up->port))
328 up->tty_break = Rx_SYS;
330 up->tty_break = Rx_BRK;
334 if (ZS_WANTS_MODEM_STATUS(up)) {
336 up->port.icount.dsr++;
342 if ((status ^ up->prev_status) ^ DCD)
343 uart_handle_dcd_change(&up->port,
345 if ((status ^ up->prev_status) ^ CTS)
346 uart_handle_cts_change(&up->port,
349 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
352 up->prev_status = status;
355 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
360 if (ZS_IS_CONS(up)) {
376 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
378 if (ZS_REGS_HELD(up)) {
379 __load_zsregs(channel, up->curregs);
380 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
383 if (ZS_TX_STOPPED(up)) {
384 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
388 if (up->port.x_char) {
389 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
390 writeb(up->port.x_char, &channel->data);
394 up->port.icount.tx++;
395 up->port.x_char = 0;
399 if (up->port.state == NULL)
401 xmit = &up->port.state->xmit;
404 if (uart_tx_stopped(&up->port))
407 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
412 uart_xmit_advance(&up->port, 1);
415 uart_write_wakeup(&up->port);
427 struct uart_ip22zilog_port *up = dev_id;
429 while (up) {
431 = ZILOG_CHANNEL_FROM_PORT(&up->port);
435 spin_lock(&up->port.lock);
445 push = ip22zilog_receive_chars(up, channel);
447 ip22zilog_status_handle(up, channel);
449 ip22zilog_transmit_chars(up, channel);
451 spin_unlock(&up->port.lock);
454 tty_flip_buffer_push(&up->port.state->port);
457 up = up->next;
458 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
461 spin_lock(&up->port.lock);
468 push = ip22zilog_receive_chars(up, channel);
470 ip22zilog_status_handle(up, channel);
472 ip22zilog_transmit_chars(up, channel);
474 spin_unlock(&up->port.lock);
477 tty_flip_buffer_push(&up->port.state->port);
479 up = up->next;
543 struct uart_ip22zilog_port *up =
560 up->curregs[R5] |= set_bits;
561 up->curregs[R5] &= ~clear_bits;
562 write_zsreg(channel, R5, up->curregs[R5]);
568 struct uart_ip22zilog_port *up =
571 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
577 struct uart_ip22zilog_port *up =
582 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
583 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
614 uart_write_wakeup(&up->port);
621 struct uart_ip22zilog_port *up = UART_ZILOG(port);
624 if (ZS_IS_CONS(up))
630 up->curregs[R1] &= ~RxINT_MASK;
631 ip22zilog_maybe_update_regs(up, channel);
637 struct uart_ip22zilog_port *up =
642 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
643 if (new_reg != up->curregs[R15]) {
644 up->curregs[R15] = new_reg;
647 write_zsreg(channel, R15, up->curregs[R15]);
654 struct uart_ip22zilog_port *up =
669 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
670 if (new_reg != up->curregs[R5]) {
671 up->curregs[R5] = new_reg;
674 write_zsreg(channel, R5, up->curregs[R5]);
680 static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
685 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
689 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
697 if (!ZS_IS_CHANNEL_A(up)) {
698 up++;
699 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
705 up->flags |= IP22ZILOG_FLAG_RESET_DONE;
706 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
709 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
713 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
715 __ip22zilog_reset(up);
717 __load_zsregs(channel, up->curregs);
719 write_zsreg(channel, R9, up->curregs[R9]);
720 up->prev_status = readb(&channel->control);
723 up->curregs[R3] |= RxENAB;
724 up->curregs[R5] |= TxENAB;
726 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
727 ip22zilog_maybe_update_regs(up, channel);
732 struct uart_ip22zilog_port *up = UART_ZILOG(port);
735 if (ZS_IS_CONS(up))
739 __ip22zilog_startup(up);
771 struct uart_ip22zilog_port *up = UART_ZILOG(port);
775 if (ZS_IS_CONS(up))
783 up->curregs[R3] &= ~RxENAB;
784 up->curregs[R5] &= ~TxENAB;
787 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
788 up->curregs[R5] &= ~SND_BRK;
789 ip22zilog_maybe_update_regs(up, channel);
798 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
802 up->curregs[R10] = NRZ;
803 up->curregs[R11] = TCBR | RCBR;
806 up->curregs[R4] &= ~XCLK_MASK;
807 up->curregs[R4] |= X16CLK;
808 up->curregs[R12] = brg & 0xff;
809 up->curregs[R13] = (brg >> 8) & 0xff;
810 up->curregs[R14] = BRENAB;
813 up->curregs[3] &= ~RxN_MASK;
814 up->curregs[5] &= ~TxN_MASK;
817 up->curregs[3] |= Rx5;
818 up->curregs[5] |= Tx5;
819 up->parity_mask = 0x1f;
822 up->curregs[3] |= Rx6;
823 up->curregs[5] |= Tx6;
824 up->parity_mask = 0x3f;
827 up->curregs[3] |= Rx7;
828 up->curregs[5] |= Tx7;
829 up->parity_mask = 0x7f;
833 up->curregs[3] |= Rx8;
834 up->curregs[5] |= Tx8;
835 up->parity_mask = 0xff;
838 up->curregs[4] &= ~0x0c;
840 up->curregs[4] |= SB2;
842 up->curregs[4] |= SB1;
844 up->curregs[4] |= PAR_ENAB;
846 up->curregs[4] &= ~PAR_ENAB;
848 up->curregs[4] |= PAR_EVEN;
850 up->curregs[4] &= ~PAR_EVEN;
852 up->port.read_status_mask = Rx_OVR;
854 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
856 up->port.read_status_mask |= BRK_ABRT;
858 up->port.ignore_status_mask = 0;
860 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
862 up->port.ignore_status_mask |= BRK_ABRT;
864 up->port.ignore_status_mask |= Rx_OVR;
868 up->port.ignore_status_mask = 0xff;
876 struct uart_ip22zilog_port *up =
883 spin_lock_irqsave(&up->port.lock, flags);
887 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
889 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
890 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
892 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
894 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
897 spin_unlock_irqrestore(&up->port.lock, flags);
1016 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1019 spin_lock_irqsave(&up->port.lock, flags);
1020 uart_console_write(&up->port, s, count, ip22zilog_put_char);
1022 spin_unlock_irqrestore(&up->port.lock, flags);
1027 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1033 up->flags |= IP22ZILOG_FLAG_IS_CONS;
1037 spin_lock_irqsave(&up->port.lock, flags);
1039 up->curregs[R15] |= BRKIE;
1041 __ip22zilog_startup(up);
1043 spin_unlock_irqrestore(&up->port.lock, flags);
1047 return uart_set_options(&up->port, con, baud, parity, bits, flow);
1078 struct uart_ip22zilog_port *up;
1089 up = &ip22zilog_port_table[0];
1091 up[channel].next = &up[channel - 1];
1092 up[channel].next = NULL;
1098 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1099 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1102 up[(chip * 2) + 0].port.mapbase =
1104 up[(chip * 2) + 1].port.mapbase =
1109 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1110 up[(chip * 2) + 0].port.irq = zilog_irq;
1111 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1112 up[(chip * 2) + 0].port.fifosize = 1;
1113 up[(chip * 2) + 0].port.has_sysrq = sysrq_on;
1114 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1115 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1116 up[(chip * 2) + 0].port.flags = 0;
1117 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1118 up[(chip * 2) + 0].flags = 0;
1121 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1122 up[(chip * 2) + 1].port.irq = zilog_irq;
1123 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1124 up[(chip * 2) + 1].port.fifosize = 1;
1125 up[(chip * 2) + 1].port.has_sysrq = sysrq_on;
1126 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1127 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1128 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1129 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1133 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1137 up->parity_mask = 0xff;
1138 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1139 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1140 up->curregs[R3] = RxENAB | Rx8;
1141 up->curregs[R5] = TxENAB | Tx8;
1142 up->curregs[R9] = NV | MIE;
1143 up->curregs[R10] = NRZ;
1144 up->curregs[R11] = TCBR | RCBR;
1146 up->curregs[R12] = (brg & 0xff);
1147 up->curregs[R13] = (brg >> 8) & 0xff;
1148 up->curregs[R14] = BRENAB;
1170 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1172 uart_add_one_port(&ip22zilog_reg, &up->port);
1191 struct uart_ip22zilog_port *up;
1194 up = &ip22zilog_port_table[i];
1196 uart_remove_one_port(&ip22zilog_reg, &up->port);
1200 up = &ip22zilog_port_table[0];
1202 if (up[(i * 2) + 0].port.mapbase) {
1203 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1204 up[(i * 2) + 0].port.mapbase = 0;
1206 if (up[(i * 2) + 1].port.mapbase) {
1207 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1208 up[(i * 2) + 1].port.mapbase = 0;