Lines Matching defs:port
3 * Freescale lpuart serial port driver
262 struct uart_port port;
382 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
384 switch (port->iotype) {
386 return readl(port->membase + off);
388 return ioread32be(port->membase + off);
394 static inline void lpuart32_write(struct uart_port *port, u32 val,
397 switch (port->iotype) {
399 writel(val, port->membase + off);
402 iowrite32be(val, port->membase + off);
440 static void lpuart_stop_tx(struct uart_port *port)
444 temp = readb(port->membase + UARTCR2);
446 writeb(temp, port->membase + UARTCR2);
449 static void lpuart32_stop_tx(struct uart_port *port)
453 temp = lpuart32_read(port, UARTCTRL);
455 lpuart32_write(port, temp, UARTCTRL);
458 static void lpuart_stop_rx(struct uart_port *port)
462 temp = readb(port->membase + UARTCR2);
463 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
466 static void lpuart32_stop_rx(struct uart_port *port)
470 temp = lpuart32_read(port, UARTCTRL);
471 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
476 struct circ_buf *xmit = &sport->port.state->xmit;
478 struct device *dev = sport->port.dev;
522 static bool lpuart_stopped_or_empty(struct uart_port *port)
524 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
531 struct circ_buf *xmit = &sport->port.state->xmit;
535 spin_lock_irqsave(&sport->port.lock, flags);
537 spin_unlock_irqrestore(&sport->port.lock, flags);
544 uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
546 spin_unlock_irqrestore(&sport->port.lock, flags);
549 uart_write_wakeup(&sport->port);
556 spin_lock_irqsave(&sport->port.lock, flags);
558 if (!lpuart_stopped_or_empty(&sport->port))
561 spin_unlock_irqrestore(&sport->port.lock, flags);
566 switch (sport->port.iotype) {
568 return sport->port.mapbase + UARTDATA;
570 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
572 return sport->port.mapbase + UARTDR;
575 static int lpuart_dma_tx_request(struct uart_port *port)
577 struct lpuart_port *sport = container_of(port,
578 struct lpuart_port, port);
589 dev_err(sport->port.dev,
599 return sport->port.iotype == UPIO_MEM32 ||
600 sport->port.iotype == UPIO_MEM32BE;
603 static void lpuart_flush_buffer(struct uart_port *port)
605 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
619 val = lpuart32_read(&sport->port, UARTFIFO);
621 lpuart32_write(&sport->port, val, UARTFIFO);
623 val = readb(sport->port.membase + UARTCFIFO);
625 writeb(val, sport->port.membase + UARTCFIFO);
629 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
632 while (!(readb(port->membase + offset) & bit))
636 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
639 while (!(lpuart32_read(port, offset) & bit))
645 static int lpuart_poll_init(struct uart_port *port)
647 struct lpuart_port *sport = container_of(port,
648 struct lpuart_port, port);
652 sport->port.fifosize = 0;
654 spin_lock_irqsave(&sport->port.lock, flags);
656 writeb(0, sport->port.membase + UARTCR2);
658 temp = readb(sport->port.membase + UARTPFIFO);
661 sport->port.membase + UARTPFIFO);
665 sport->port.membase + UARTCFIFO);
668 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
669 readb(sport->port.membase + UARTDR);
670 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
673 writeb(0, sport->port.membase + UARTTWFIFO);
674 writeb(1, sport->port.membase + UARTRWFIFO);
677 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
678 spin_unlock_irqrestore(&sport->port.lock, flags);
683 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
686 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
687 writeb(c, port->membase + UARTDR);
690 static int lpuart_poll_get_char(struct uart_port *port)
692 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
695 return readb(port->membase + UARTDR);
698 static int lpuart32_poll_init(struct uart_port *port)
701 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
704 sport->port.fifosize = 0;
706 spin_lock_irqsave(&sport->port.lock, flags);
709 lpuart32_write(&sport->port, 0, UARTCTRL);
711 temp = lpuart32_read(&sport->port, UARTFIFO);
714 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
717 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
720 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
721 lpuart32_read(&sport->port, UARTDATA);
722 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
726 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
727 spin_unlock_irqrestore(&sport->port.lock, flags);
732 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
734 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
735 lpuart32_write(port, c, UARTDATA);
738 static int lpuart32_poll_get_char(struct uart_port *port)
740 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
743 return lpuart32_read(port, UARTDATA);
749 struct uart_port *port = &sport->port;
752 uart_port_tx(port, ch,
753 readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
754 writeb(ch, port->membase + UARTDR));
759 struct circ_buf *xmit = &sport->port.state->xmit;
762 if (sport->port.x_char) {
763 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
764 sport->port.icount.tx++;
765 sport->port.x_char = 0;
769 if (lpuart_stopped_or_empty(&sport->port)) {
770 lpuart32_stop_tx(&sport->port);
774 txcnt = lpuart32_read(&sport->port, UARTWATER);
778 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
779 uart_xmit_advance(&sport->port, 1);
780 txcnt = lpuart32_read(&sport->port, UARTWATER);
786 uart_write_wakeup(&sport->port);
789 lpuart32_stop_tx(&sport->port);
792 static void lpuart_start_tx(struct uart_port *port)
794 struct lpuart_port *sport = container_of(port,
795 struct lpuart_port, port);
798 temp = readb(port->membase + UARTCR2);
799 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
802 if (!lpuart_stopped_or_empty(port))
805 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
810 static void lpuart32_start_tx(struct uart_port *port)
812 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
816 if (!lpuart_stopped_or_empty(port))
819 temp = lpuart32_read(port, UARTCTRL);
820 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
822 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
828 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
832 pm_runtime_mark_last_busy(port->dev);
833 pm_runtime_put_autosuspend(port->dev);
836 pm_runtime_get_sync(port->dev);
842 static unsigned int lpuart_tx_empty(struct uart_port *port)
844 struct lpuart_port *sport = container_of(port,
845 struct lpuart_port, port);
846 unsigned char sr1 = readb(port->membase + UARTSR1);
847 unsigned char sfifo = readb(port->membase + UARTSFIFO);
858 static unsigned int lpuart32_tx_empty(struct uart_port *port)
860 struct lpuart_port *sport = container_of(port,
861 struct lpuart_port, port);
862 unsigned long stat = lpuart32_read(port, UARTSTAT);
863 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
864 unsigned long ctrl = lpuart32_read(port, UARTCTRL);
882 spin_lock(&sport->port.lock);
884 spin_unlock(&sport->port.lock);
890 struct tty_port *port = &sport->port.state->port;
893 spin_lock(&sport->port.lock);
895 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
897 sport->port.icount.rx++;
902 sr = readb(sport->port.membase + UARTSR1);
903 rx = readb(sport->port.membase + UARTDR);
905 if (uart_prepare_sysrq_char(&sport->port, rx))
910 sport->port.icount.parity++;
912 sport->port.icount.frame++;
917 if (sr & sport->port.ignore_status_mask) {
923 sr &= sport->port.read_status_mask;
933 sport->port.sysrq = 0;
936 if (tty_insert_flip_char(port, rx, flg) == 0)
937 sport->port.icount.buf_overrun++;
942 sport->port.icount.overrun += overrun;
948 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
949 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
952 uart_unlock_and_check_sysrq(&sport->port);
954 tty_flip_buffer_push(port);
959 spin_lock(&sport->port.lock);
961 spin_unlock(&sport->port.lock);
967 struct tty_port *port = &sport->port.state->port;
971 spin_lock(&sport->port.lock);
973 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
975 sport->port.icount.rx++;
980 sr = lpuart32_read(&sport->port, UARTSTAT);
981 rx = lpuart32_read(&sport->port, UARTDATA);
990 if (is_break && uart_handle_break(&sport->port))
993 if (uart_prepare_sysrq_char(&sport->port, rx))
998 sport->port.icount.parity++;
1001 sport->port.icount.brk++;
1003 sport->port.icount.frame++;
1007 sport->port.icount.overrun++;
1009 if (sr & sport->port.ignore_status_mask) {
1015 sr &= sport->port.read_status_mask;
1033 if (tty_insert_flip_char(port, rx, flg) == 0)
1034 sport->port.icount.buf_overrun++;
1038 uart_unlock_and_check_sysrq(&sport->port);
1040 tty_flip_buffer_push(port);
1048 sts = readb(sport->port.membase + UARTSR1);
1052 readb(sport->port.membase + UARTDR);
1053 uart_handle_break(&sport->port);
1055 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1068 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1072 if (*p && uart_handle_sysrq_char(port, *p))
1085 lpuart_handle_sysrq_chars(&sport->port,
1092 lpuart_handle_sysrq_chars(&sport->port,
1098 static int lpuart_tty_insert_flip_string(struct tty_port *port,
1106 return tty_insert_flip_string(port, chars, size);
1111 struct tty_port *port = &sport->port.state->port;
1120 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1124 lpuart32_write(&sport->port, sr, UARTSTAT);
1127 sport->port.icount.parity++;
1129 sport->port.icount.frame++;
1132 unsigned char sr = readb(sport->port.membase + UARTSR1);
1138 cr2 = readb(sport->port.membase + UARTCR2);
1140 writeb(cr2, sport->port.membase + UARTCR2);
1143 readb(sport->port.membase + UARTDR);
1146 sport->port.icount.parity++;
1148 sport->port.icount.frame++;
1158 if (readb(sport->port.membase + UARTSFIFO) &
1161 sport->port.membase + UARTSFIFO);
1163 sport->port.membase + UARTCFIFO);
1167 writeb(cr2, sport->port.membase + UARTCR2);
1173 spin_lock_irqsave(&sport->port.lock, flags);
1177 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1178 spin_unlock_irqrestore(&sport->port.lock, flags);
1199 if (sport->port.sysrq) {
1219 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1222 sport->port.icount.buf_overrun++;
1224 sport->port.icount.rx += copied;
1230 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1233 sport->port.icount.buf_overrun++;
1238 sport->port.icount.rx += copied;
1247 spin_unlock_irqrestore(&sport->port.lock, flags);
1249 tty_flip_buffer_push(port);
1271 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1288 sts = lpuart32_read(&sport->port, UARTSTAT);
1289 rxcount = lpuart32_read(&sport->port, UARTWATER);
1301 lpuart32_write(&sport->port, sts, UARTSTAT);
1324 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1338 if (spin_trylock_irqsave(&sport->port.lock, flags)) {
1340 spin_unlock_irqrestore(&sport->port.lock, flags);
1349 struct tty_port *port = &sport->port.state->port;
1350 struct tty_struct *tty = port->tty;
1374 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL);
1385 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1396 dev_err(sport->port.dev,
1408 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1418 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1420 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1423 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL);
1425 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL);
1428 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1429 sport->port.membase + UARTCR5);
1435 static void lpuart_dma_rx_free(struct uart_port *port)
1437 struct lpuart_port *sport = container_of(port,
1438 struct lpuart_port, port);
1453 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1456 struct lpuart_port *sport = container_of(port,
1457 struct lpuart_port, port);
1459 u8 modem = readb(sport->port.membase + UARTMODEM) &
1461 writeb(modem, sport->port.membase + UARTMODEM);
1479 writeb(modem, sport->port.membase + UARTMODEM);
1483 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1486 struct lpuart_port *sport = container_of(port,
1487 struct lpuart_port, port);
1489 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1491 lpuart32_write(&sport->port, modem, UARTMODIR);
1509 lpuart32_write(&sport->port, modem, UARTMODIR);
1513 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1518 reg = readb(port->membase + UARTCR1);
1525 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1530 reg = lpuart32_read(port, UARTCTRL);
1537 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1541 reg = readb(port->membase + UARTCR1);
1548 writeb(reg, port->membase + UARTCR1);
1551 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1555 reg = lpuart32_read(port, UARTCTRL);
1562 lpuart32_write(port, reg, UARTCTRL);
1565 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1569 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1574 writeb(temp, port->membase + UARTCR2);
1577 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1581 temp = lpuart32_read(port, UARTCTRL);
1599 lpuart32_write(port, temp, UARTCTRL);
1601 lpuart32_write(port, temp, UARTCTRL);
1605 lpuart32_write(port, temp, UARTCTRL);
1607 lpuart32_write(port, temp, UARTCTRL);
1616 cr2 = readb(sport->port.membase + UARTCR2);
1620 writeb(cr2, sport->port.membase + UARTCR2);
1622 val = readb(sport->port.membase + UARTPFIFO);
1624 sport->port.membase + UARTPFIFO);
1628 sport->port.membase + UARTCFIFO);
1631 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1632 readb(sport->port.membase + UARTDR);
1633 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1636 if (uart_console(&sport->port))
1638 writeb(0, sport->port.membase + UARTTWFIFO);
1639 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1642 writeb(cr2_saved, sport->port.membase + UARTCR2);
1651 cr2 = readb(sport->port.membase + UARTCR2);
1653 writeb(cr2, sport->port.membase + UARTCR2);
1661 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1665 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1668 val = lpuart32_read(&sport->port, UARTFIFO);
1672 lpuart32_write(&sport->port, val, UARTFIFO);
1675 if (uart_console(&sport->port))
1679 lpuart32_write(&sport->port, val, UARTWATER);
1682 if (!uart_console(&sport->port)) {
1683 val = lpuart32_read(&sport->port, UARTMODIR);
1685 lpuart32_write(&sport->port, val, UARTMODIR);
1689 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1698 temp = lpuart32_read(&sport->port, UARTCTRL);
1701 lpuart32_write(&sport->port, temp, UARTCTRL);
1716 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1718 dev_dbg_once(sport->port.dev,
1724 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1726 dev_dbg_once(sport->port.dev,
1738 if (uart_console(&sport->port))
1744 ret = lpuart_dma_tx_request(&sport->port);
1751 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1752 lpuart32_write(&sport->port,
1755 writeb(readb(sport->port.membase + UARTCR5) |
1756 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1770 if (uart_console(&sport->port))
1789 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1790 cr3 = readb(sport->port.membase + UARTCR3);
1792 writeb(cr3, sport->port.membase + UARTCR3);
1805 spin_lock_irqsave(&sport->port.lock, flags);
1812 spin_unlock_irqrestore(&sport->port.lock, flags);
1815 static int lpuart_startup(struct uart_port *port)
1817 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1821 temp = readb(sport->port.membase + UARTPFIFO);
1825 sport->port.fifosize = sport->txfifo_size;
1840 temp = lpuart32_read(&sport->port, UARTCTRL);
1843 lpuart32_write(&sport->port, temp, UARTCTRL);
1850 temp = lpuart32_read(&sport->port, UARTCTRL);
1855 lpuart32_write(&sport->port, temp, UARTCTRL);
1862 spin_lock_irqsave(&sport->port.lock, flags);
1872 spin_unlock_irqrestore(&sport->port.lock, flags);
1875 static int lpuart32_startup(struct uart_port *port)
1877 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1881 temp = lpuart32_read(&sport->port, UARTFIFO);
1885 sport->port.fifosize = sport->txfifo_size;
1898 sport->port.fifosize = sport->txfifo_size;
1910 lpuart_dma_rx_free(&sport->port);
1929 static void lpuart_shutdown(struct uart_port *port)
1931 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1935 spin_lock_irqsave(&port->lock, flags);
1938 temp = readb(port->membase + UARTCR2);
1941 writeb(temp, port->membase + UARTCR2);
1943 spin_unlock_irqrestore(&port->lock, flags);
1948 static void lpuart32_shutdown(struct uart_port *port)
1951 container_of(port, struct lpuart_port, port);
1955 spin_lock_irqsave(&port->lock, flags);
1958 temp = lpuart32_read(&sport->port, UARTSTAT);
1959 lpuart32_write(&sport->port, temp, UARTSTAT);
1962 temp = lpuart32_read(port, UARTBAUD);
1964 lpuart32_write(port, temp, UARTBAUD);
1967 temp = lpuart32_read(port, UARTCTRL);
1970 lpuart32_write(port, temp, UARTCTRL);
1972 spin_unlock_irqrestore(&port->lock, flags);
1978 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1981 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1988 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1989 old_cr2 = readb(sport->port.membase + UARTCR2);
1990 cr3 = readb(sport->port.membase + UARTCR3);
1991 cr4 = readb(sport->port.membase + UARTCR4);
1992 bdh = readb(sport->port.membase + UARTBDH);
1993 modem = readb(sport->port.membase + UARTMODEM);
2025 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2060 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
2066 * Since timer function acqures sport->port.lock, need to stop before
2070 lpuart_dma_rx_free(&sport->port);
2072 spin_lock_irqsave(&sport->port.lock, flags);
2074 sport->port.read_status_mask = 0;
2076 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
2078 sport->port.read_status_mask |= UARTSR1_FE;
2081 sport->port.ignore_status_mask = 0;
2083 sport->port.ignore_status_mask |= UARTSR1_PE;
2085 sport->port.ignore_status_mask |= UARTSR1_FE;
2091 sport->port.ignore_status_mask |= UARTSR1_OR;
2094 /* update the per-port timeout */
2095 uart_update_timeout(port, termios->c_cflag, baud);
2098 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2102 sport->port.membase + UARTCR2);
2104 sbr = sport->port.uartclk / (16 * baud);
2105 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
2110 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2111 writeb(bdh, sport->port.membase + UARTBDH);
2112 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2113 writeb(cr3, sport->port.membase + UARTCR3);
2114 writeb(cr1, sport->port.membase + UARTCR1);
2115 writeb(modem, sport->port.membase + UARTMODEM);
2118 writeb(old_cr2, sport->port.membase + UARTCR2);
2127 spin_unlock_irqrestore(&sport->port.lock, flags);
2130 static void __lpuart32_serial_setbrg(struct uart_port *port,
2135 u32 clk = port->uartclk;
2184 dev_warn(port->dev,
2187 tmp = lpuart32_read(port, UARTBAUD);
2203 lpuart32_write(port, tmp, UARTBAUD);
2209 __lpuart32_serial_setbrg(&sport->port, baudrate,
2216 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2219 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2225 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2226 bd = lpuart32_read(&sport->port, UARTBAUD);
2227 modem = lpuart32_read(&sport->port, UARTMODIR);
2260 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2295 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2301 * Since timer function acqures sport->port.lock, need to stop before
2305 lpuart_dma_rx_free(&sport->port);
2307 spin_lock_irqsave(&sport->port.lock, flags);
2309 sport->port.read_status_mask = 0;
2311 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2313 sport->port.read_status_mask |= UARTSTAT_FE;
2316 sport->port.ignore_status_mask = 0;
2318 sport->port.ignore_status_mask |= UARTSTAT_PE;
2320 sport->port.ignore_status_mask |= UARTSTAT_FE;
2326 sport->port.ignore_status_mask |= UARTSTAT_OR;
2329 /* update the per-port timeout */
2330 uart_update_timeout(port, termios->c_cflag, baud);
2338 lpuart32_write(&sport->port, 0, UARTMODIR);
2339 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2343 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2346 lpuart32_write(&sport->port, bd, UARTBAUD);
2348 lpuart32_write(&sport->port, modem, UARTMODIR);
2349 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2362 spin_unlock_irqrestore(&sport->port.lock, flags);
2365 static const char *lpuart_type(struct uart_port *port)
2370 static void lpuart_release_port(struct uart_port *port)
2375 static int lpuart_request_port(struct uart_port *port)
2380 /* configure/autoconfigure the port */
2381 static void lpuart_config_port(struct uart_port *port, int flags)
2384 port->type = PORT_LPUART;
2387 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2393 if (port->irq != ser->irq)
2397 if (port->uartclk / 16 != ser->baud_base)
2399 if (port->iobase != ser->port)
2459 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2461 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2462 writeb(ch, port->membase + UARTDR);
2465 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2467 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2468 lpuart32_write(port, ch, UARTDATA);
2480 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2482 spin_lock_irqsave(&sport->port.lock, flags);
2485 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2488 writeb(cr2, sport->port.membase + UARTCR2);
2490 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2493 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2495 writeb(old_cr2, sport->port.membase + UARTCR2);
2498 spin_unlock_irqrestore(&sport->port.lock, flags);
2510 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2512 spin_lock_irqsave(&sport->port.lock, flags);
2515 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2518 lpuart32_write(&sport->port, cr, UARTCTRL);
2520 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2523 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2525 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2528 spin_unlock_irqrestore(&sport->port.lock, flags);
2532 * if the port was already initialised (eg, by a boot loader),
2542 cr = readb(sport->port.membase + UARTCR2);
2547 /* ok, the port was enabled */
2549 cr = readb(sport->port.membase + UARTCR1);
2564 bdh = readb(sport->port.membase + UARTBDH);
2566 bdl = readb(sport->port.membase + UARTBDL);
2570 brfa = readb(sport->port.membase + UARTCR4);
2580 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2591 cr = lpuart32_read(&sport->port, UARTCTRL);
2596 /* ok, the port was enabled */
2598 cr = lpuart32_read(&sport->port, UARTCTRL);
2613 bd = lpuart32_read(&sport->port, UARTBAUD);
2626 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2640 * if so, search for the first available port that does have
2663 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2691 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2698 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2704 if (!device->port.membase)
2714 if (!device->port.membase)
2717 if (device->port.iotype != UPIO_MEM32)
2718 device->port.iotype = UPIO_MEM32BE;
2729 if (!device->port.membase)
2732 device->port.iotype = UPIO_MEM32;
2736 if (device->port.uartclk && device->baud)
2737 __lpuart32_serial_setbrg(&device->port, device->baud,
2741 cr = lpuart32_read(&device->port, UARTCTRL);
2743 lpuart32_write(&device->port, cr, UARTCTRL);
2751 if (!device->port.membase)
2754 device->port.iotype = UPIO_MEM32;
2755 device->port.membase += IMX_REG_OFF;
2792 struct uart_port *port = &sport->port;
2800 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2809 ctrl = lpuart32_read(port, UARTCTRL);
2811 bd = lpuart32_read(&sport->port, UARTBAUD);
2813 port)) {
2814 dev_warn(sport->port.dev,
2821 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2829 lpuart32_write(port, bd, UARTBAUD);
2830 lpuart32_write(port, ctrl, UARTCTRL);
2851 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2852 if (IS_ERR(sport->port.membase))
2853 return PTR_ERR(sport->port.membase);
2855 sport->port.membase += sdata->reg_off;
2856 sport->port.mapbase = res->start + sdata->reg_off;
2857 sport->port.dev = &pdev->dev;
2858 sport->port.type = PORT_LPUART;
2866 sport->port.irq = ret;
2867 sport->port.iotype = sdata->iotype;
2869 sport->port.ops = &lpuart32_pops;
2871 sport->port.ops = &lpuart_pops;
2872 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2873 sport->port.flags = UPF_BOOT_AUTOCONF;
2876 sport->port.rs485_config = lpuart32_config_rs485;
2878 sport->port.rs485_config = lpuart_config_rs485;
2879 sport->port.rs485_supported = lpuart_rs485_supported;
2907 sport->port.line = ret;
2912 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2914 lpuart_ports[sport->port.line] = sport;
2916 platform_set_drvdata(pdev, &sport->port);
2935 ret = uart_get_rs485_mode(&sport->port);
2939 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2943 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2951 uart_remove_one_port(&lpuart_reg, &sport->port);
2966 uart_remove_one_port(&lpuart_reg, &sport->port);
3005 val = lpuart32_read(&sport->port, UARTCTRL);
3006 baud = lpuart32_read(&sport->port, UARTBAUD);
3009 lpuart32_write(&sport->port, 0, UARTWATER);
3012 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
3018 lpuart32_write(&sport->port, val, UARTCTRL);
3019 lpuart32_write(&sport->port, baud, UARTBAUD);
3021 val = readb(sport->port.membase + UARTCR2);
3026 writeb(val, sport->port.membase + UARTCR2);
3032 struct tty_port *port = &sport->port.state->port;
3037 tty = tty_port_tty_get(port);
3044 if ((tty_port_initialized(port) && may_wake) ||
3045 (!console_suspend_enabled && uart_console(&sport->port)))
3054 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
3076 val = lpuart32_read(&sport->port, UARTSTAT);
3077 lpuart32_write(&sport->port, val, UARTSTAT);
3089 uart_suspend_port(&lpuart_reg, &sport->port);
3092 spin_lock_irqsave(&sport->port.lock, flags);
3095 temp = lpuart32_read(&sport->port, UARTCTRL);
3097 lpuart32_write(&sport->port, temp, UARTCTRL);
3100 temp = readb(sport->port.membase + UARTCR2);
3102 writeb(temp, sport->port.membase + UARTCR2);
3104 spin_unlock_irqrestore(&sport->port.lock, flags);
3109 * non-idle DMA channels. If port wakeup is enabled or if port
3110 * is console port or 'no_console_suspend' is set the Rx DMA
3114 lpuart_dma_rx_free(&sport->port);
3116 /* Disable Rx DMA to use UART port as wakeup source */
3117 spin_lock_irqsave(&sport->port.lock, flags);
3119 temp = lpuart32_read(&sport->port, UARTBAUD);
3120 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
3123 writeb(readb(sport->port.membase + UARTCR5) &
3124 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3126 spin_unlock_irqrestore(&sport->port.lock, flags);
3130 spin_lock_irqsave(&sport->port.lock, flags);
3132 temp = lpuart32_read(&sport->port, UARTBAUD);
3134 lpuart32_write(&sport->port, temp, UARTBAUD);
3136 temp = readb(sport->port.membase + UARTCR5);
3138 writeb(temp, sport->port.membase + UARTCR5);
3140 spin_unlock_irqrestore(&sport->port.lock, flags);
3144 } else if (pm_runtime_active(sport->port.dev)) {
3146 pm_runtime_disable(sport->port.dev);
3147 pm_runtime_set_suspended(sport->port.dev);
3155 struct tty_port *port = &sport->port.state->port;
3156 struct uart_port *uport = &sport->port;
3160 * all lost no matter the port is wakeup source.
3161 * For console port, console baud rate setting lost and print messy
3162 * log when enable the console port as wakeup source. To avoid the
3163 * issue happen, user should not enable uart port as wakeup source
3167 console_suspend_enabled && uart_console(&sport->port)) {
3169 mutex_lock(&port->mutex);
3172 if (port->tty && termios.c_cflag == 0)
3173 termios = port->tty->termios;
3175 mutex_unlock(&port->mutex);
3189 } else if (pm_runtime_active(sport->port.dev)) {
3193 pm_runtime_set_active(sport->port.dev);
3194 pm_runtime_enable(sport->port.dev);
3198 uart_resume_port(&lpuart_reg, &sport->port);
3244 MODULE_DESCRIPTION("Freescale lpuart serial port driver");