Lines Matching refs:val
90 unsigned int val;
92 val = bcm_uart_readl(port, UART_IR_REG);
93 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
101 unsigned int val;
103 val = bcm_uart_readl(port, UART_MCTL_REG);
104 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
107 val |= UART_MCTL_DTR_MASK;
109 val |= UART_MCTL_RTS_MASK;
110 bcm_uart_writel(port, val, UART_MCTL_REG);
112 val = bcm_uart_readl(port, UART_CTL_REG);
114 val |= UART_CTL_LOOPBACK_MASK;
116 val &= ~UART_CTL_LOOPBACK_MASK;
117 bcm_uart_writel(port, val, UART_CTL_REG);
125 unsigned int val, mctrl;
128 val = bcm_uart_readl(port, UART_EXTINP_REG);
129 if (val & UART_EXTINP_RI_MASK)
131 if (val & UART_EXTINP_CTS_MASK)
133 if (val & UART_EXTINP_DCD_MASK)
135 if (val & UART_EXTINP_DSR_MASK)
145 unsigned int val;
147 val = bcm_uart_readl(port, UART_CTL_REG);
148 val &= ~(UART_CTL_TXEN_MASK);
149 bcm_uart_writel(port, val, UART_CTL_REG);
151 val = bcm_uart_readl(port, UART_IR_REG);
152 val &= ~UART_TX_INT_MASK;
153 bcm_uart_writel(port, val, UART_IR_REG);
161 unsigned int val;
163 val = bcm_uart_readl(port, UART_IR_REG);
164 val |= UART_TX_INT_MASK;
165 bcm_uart_writel(port, val, UART_IR_REG);
167 val = bcm_uart_readl(port, UART_CTL_REG);
168 val |= UART_CTL_TXEN_MASK;
169 bcm_uart_writel(port, val, UART_CTL_REG);
177 unsigned int val;
179 val = bcm_uart_readl(port, UART_IR_REG);
180 val &= ~UART_RX_INT_MASK;
181 bcm_uart_writel(port, val, UART_IR_REG);
189 unsigned int val;
191 val = bcm_uart_readl(port, UART_IR_REG);
192 val |= UART_IR_MASK(UART_IR_EXTIP);
193 bcm_uart_writel(port, val, UART_IR_REG);
202 unsigned int val;
206 val = bcm_uart_readl(port, UART_CTL_REG);
208 val |= UART_CTL_XMITBRK_MASK;
210 val &= ~UART_CTL_XMITBRK_MASK;
211 bcm_uart_writel(port, val, UART_CTL_REG);
245 unsigned int val;
249 val = bcm_uart_readl(port, UART_CTL_REG);
250 val |= UART_CTL_RSTRXFIFO_MASK;
251 bcm_uart_writel(port, val, UART_CTL_REG);
306 unsigned int val;
310 val = bcm_uart_readl(port, UART_MCTL_REG);
311 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
313 pending = uart_port_tx_limited(port, ch, port->fifosize - val,
321 val = bcm_uart_readl(port, UART_IR_REG);
322 val &= ~UART_TX_INT_MASK;
323 bcm_uart_writel(port, val, UART_IR_REG);
365 unsigned int val;
367 val = bcm_uart_readl(port, UART_CTL_REG);
368 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
369 bcm_uart_writel(port, val, UART_CTL_REG);
377 unsigned int val;
379 val = bcm_uart_readl(port, UART_CTL_REG);
380 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
382 bcm_uart_writel(port, val, UART_CTL_REG);
390 unsigned int val;
393 val = bcm_uart_readl(port, UART_CTL_REG);
394 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
395 bcm_uart_writel(port, val, UART_CTL_REG);
407 unsigned int val;
419 val = bcm_uart_readl(port, UART_MCTL_REG);
420 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
421 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
422 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
423 bcm_uart_writel(port, val, UART_MCTL_REG);
426 val = bcm_uart_readl(port, UART_CTL_REG);
427 val &= ~UART_CTL_RXTMOUTCNT_MASK;
428 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
429 bcm_uart_writel(port, val, UART_CTL_REG);
432 val = UART_EXTINP_INT_MASK;
433 val |= UART_EXTINP_DCD_NOSENSE_MASK;
434 val |= UART_EXTINP_CTS_NOSENSE_MASK;
435 bcm_uart_writel(port, val, UART_EXTINP_REG);
605 unsigned int val;
607 val = bcm_uart_readl(port, UART_MCTL_REG);
608 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
609 return !(port->fifosize - val);
667 unsigned int val;
669 val = bcm_uart_readl(port, UART_IR_REG);
670 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
679 unsigned int val;
681 val = bcm_uart_readl(port, UART_EXTINP_REG);
682 if (val & UART_EXTINP_CTS_MASK)