Lines Matching defs:uap
279 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
282 return uap->reg_offset[reg];
285 static unsigned int pl011_read(const struct uart_amba_port *uap,
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
290 return (uap->port.iotype == UPIO_MEM32) ?
294 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
299 if (uap->port.iotype == UPIO_MEM32)
310 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
318 status = pl011_read(uap, REG_FR);
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
325 uap->port.icount.rx++;
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
334 uap->port.icount.parity++;
336 uap->port.icount.frame++;
338 uap->port.icount.overrun++;
340 ch &= uap->port.read_status_mask;
350 spin_unlock(&uap->port.lock);
351 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
352 spin_lock(&uap->port.lock);
355 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
392 static void pl011_dma_probe(struct uart_amba_port *uap)
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
396 struct device *dev = uap->port.dev;
398 .dst_addr = uap->port.mapbase +
399 pl011_reg_to_offset(uap, REG_DR),
402 .dst_maxburst = uap->fifosize >> 1,
408 uap->dma_probed = true;
412 uap->dma_probed = false;
418 dev_info(uap->port.dev, "no DMA platform data\n");
429 dev_err(uap->port.dev, "no TX DMA channel!\n");
435 uap->dmatx.chan = chan;
437 dev_info(uap->port.dev, "DMA channel TX %s\n",
438 dma_chan_name(uap->dmatx.chan));
447 dev_err(uap->port.dev, "no RX DMA channel!\n");
454 .src_addr = uap->port.mapbase +
455 pl011_reg_to_offset(uap, REG_DR),
458 .src_maxburst = uap->fifosize >> 2,
472 dev_info(uap->port.dev,
478 uap->dmarx.chan = chan;
480 uap->dmarx.auto_poll_rate = false;
484 uap->dmarx.auto_poll_rate = false;
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
492 uap->dmarx.auto_poll_rate = true;
493 uap->dmarx.poll_rate = 100;
497 uap->dmarx.poll_timeout =
500 uap->dmarx.poll_timeout = 3000;
502 uap->dmarx.auto_poll_rate = of_property_read_bool(
504 if (uap->dmarx.auto_poll_rate) {
509 uap->dmarx.poll_rate = x;
511 uap->dmarx.poll_rate = 100;
514 uap->dmarx.poll_timeout = x;
516 uap->dmarx.poll_timeout = 3000;
519 dev_info(uap->port.dev, "DMA channel RX %s\n",
520 dma_chan_name(uap->dmarx.chan));
524 static void pl011_dma_remove(struct uart_amba_port *uap)
526 if (uap->dmatx.chan)
527 dma_release_channel(uap->dmatx.chan);
528 if (uap->dmarx.chan)
529 dma_release_channel(uap->dmarx.chan);
533 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
534 static void pl011_start_tx_pio(struct uart_amba_port *uap);
542 struct uart_amba_port *uap = data;
543 struct pl011_dmatx_data *dmatx = &uap->dmatx;
547 spin_lock_irqsave(&uap->port.lock, flags);
548 if (uap->dmatx.queued)
552 dmacr = uap->dmacr;
553 uap->dmacr = dmacr & ~UART011_TXDMAE;
554 pl011_write(uap->dmacr, uap, REG_DMACR);
565 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
566 uart_circ_empty(&uap->port.state->xmit)) {
567 uap->dmatx.queued = false;
568 spin_unlock_irqrestore(&uap->port.lock, flags);
572 if (pl011_dma_tx_refill(uap) <= 0)
577 pl011_start_tx_pio(uap);
579 spin_unlock_irqrestore(&uap->port.lock, flags);
590 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
592 struct pl011_dmatx_data *dmatx = &uap->dmatx;
596 struct circ_buf *xmit = &uap->port.state->xmit;
606 if (count < (uap->fifosize >> 1)) {
607 uap->dmatx.queued = false;
640 uap->dmatx.queued = false;
641 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
649 uap->dmatx.queued = false;
654 dev_dbg(uap->port.dev, "TX DMA busy\n");
660 desc->callback_param = uap;
668 uap->dmacr |= UART011_TXDMAE;
669 pl011_write(uap->dmacr, uap, REG_DMACR);
670 uap->dmatx.queued = true;
676 uart_xmit_advance(&uap->port, count);
679 uart_write_wakeup(&uap->port);
692 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
694 if (!uap->using_tx_dma)
702 if (uap->dmatx.queued) {
703 uap->dmacr |= UART011_TXDMAE;
704 pl011_write(uap->dmacr, uap, REG_DMACR);
705 uap->im &= ~UART011_TXIM;
706 pl011_write(uap->im, uap, REG_IMSC);
714 if (pl011_dma_tx_refill(uap) > 0) {
715 uap->im &= ~UART011_TXIM;
716 pl011_write(uap->im, uap, REG_IMSC);
726 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
728 if (uap->dmatx.queued) {
729 uap->dmacr &= ~UART011_TXDMAE;
730 pl011_write(uap->dmacr, uap, REG_DMACR);
742 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
746 if (!uap->using_tx_dma)
749 if (!uap->port.x_char) {
753 if (!uap->dmatx.queued) {
754 if (pl011_dma_tx_refill(uap) > 0) {
755 uap->im &= ~UART011_TXIM;
756 pl011_write(uap->im, uap, REG_IMSC);
759 } else if (!(uap->dmacr & UART011_TXDMAE)) {
760 uap->dmacr |= UART011_TXDMAE;
761 pl011_write(uap->dmacr, uap, REG_DMACR);
770 dmacr = uap->dmacr;
771 uap->dmacr &= ~UART011_TXDMAE;
772 pl011_write(uap->dmacr, uap, REG_DMACR);
774 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
783 pl011_write(uap->port.x_char, uap, REG_DR);
784 uap->port.icount.tx++;
785 uap->port.x_char = 0;
788 uap->dmacr = dmacr;
789 pl011_write(dmacr, uap, REG_DMACR);
799 __releases(&uap->port.lock)
800 __acquires(&uap->port.lock)
802 struct uart_amba_port *uap =
805 if (!uap->using_tx_dma)
808 dmaengine_terminate_async(uap->dmatx.chan);
810 if (uap->dmatx.queued) {
811 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
812 uap->dmatx.len, DMA_TO_DEVICE);
813 uap->dmatx.queued = false;
814 uap->dmacr &= ~UART011_TXDMAE;
815 pl011_write(uap->dmacr, uap, REG_DMACR);
821 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
823 struct dma_chan *rxchan = uap->dmarx.chan;
824 struct pl011_dmarx_data *dmarx = &uap->dmarx;
832 dbuf = uap->dmarx.use_buf_b ?
833 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
843 uap->dmarx.running = false;
850 desc->callback_param = uap;
854 uap->dmacr |= UART011_RXDMAE;
855 pl011_write(uap->dmacr, uap, REG_DMACR);
856 uap->dmarx.running = true;
858 uap->im &= ~UART011_RXIM;
859 pl011_write(uap->im, uap, REG_IMSC);
867 * with the port spinlock uap->port.lock held.
869 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
873 struct tty_port *port = &uap->port.state->port;
875 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
879 struct pl011_dmarx_data *dmarx = &uap->dmarx;
882 if (uap->dmarx.poll_rate) {
901 uap->port.icount.rx += dma_count;
903 dev_warn(uap->port.dev,
908 if (uap->dmarx.poll_rate)
918 UART011_FEIS, uap, REG_ICR);
931 fifotaken = pl011_fifo_to_tty(uap);
934 dev_vdbg(uap->port.dev,
940 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
942 struct pl011_dmarx_data *dmarx = &uap->dmarx;
956 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
960 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
963 uap->dmacr &= ~UART011_RXDMAE;
964 pl011_write(uap->dmacr, uap, REG_DMACR);
965 uap->dmarx.running = false;
976 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
980 if (pl011_dma_rx_trigger_dma(uap)) {
981 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
983 uap->im |= UART011_RXIM;
984 pl011_write(uap->im, uap, REG_IMSC);
990 struct uart_amba_port *uap = data;
991 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1007 spin_lock_irq(&uap->port.lock);
1018 uap->dmarx.running = false;
1020 ret = pl011_dma_rx_trigger_dma(uap);
1022 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1023 spin_unlock_irq(&uap->port.lock);
1029 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1031 uap->im |= UART011_RXIM;
1032 pl011_write(uap->im, uap, REG_IMSC);
1041 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1043 if (!uap->using_rx_dma)
1047 uap->dmacr &= ~UART011_RXDMAE;
1048 pl011_write(uap->dmacr, uap, REG_DMACR);
1058 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1059 struct tty_port *port = &uap->port.state->port;
1060 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1061 struct dma_chan *rxchan = uap->dmarx.chan;
1069 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
1087 > uap->dmarx.poll_timeout) {
1089 spin_lock_irqsave(&uap->port.lock, flags);
1090 pl011_dma_rx_stop(uap);
1091 uap->im |= UART011_RXIM;
1092 pl011_write(uap->im, uap, REG_IMSC);
1093 spin_unlock_irqrestore(&uap->port.lock, flags);
1095 uap->dmarx.running = false;
1097 del_timer(&uap->dmarx.timer);
1099 mod_timer(&uap->dmarx.timer,
1100 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1104 static void pl011_dma_startup(struct uart_amba_port *uap)
1108 if (!uap->dma_probed)
1109 pl011_dma_probe(uap);
1111 if (!uap->dmatx.chan)
1114 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1115 if (!uap->dmatx.buf) {
1116 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1117 uap->port.fifosize = uap->fifosize;
1121 uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
1124 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1125 uap->using_tx_dma = true;
1127 if (!uap->dmarx.chan)
1131 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1134 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1139 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,
1142 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1144 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1149 uap->using_rx_dma = true;
1153 uap->dmacr |= UART011_DMAONERR;
1154 pl011_write(uap->dmacr, uap, REG_DMACR);
1161 if (uap->vendor->dma_threshold)
1163 uap, REG_ST_DMAWM);
1165 if (uap->using_rx_dma) {
1166 if (pl011_dma_rx_trigger_dma(uap))
1167 dev_dbg(uap->port.dev, "could not trigger initial "
1169 if (uap->dmarx.poll_rate) {
1170 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1171 mod_timer(&uap->dmarx.timer,
1173 msecs_to_jiffies(uap->dmarx.poll_rate));
1174 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1175 uap->dmarx.last_jiffies = jiffies;
1180 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1182 if (!(uap->using_tx_dma || uap->using_rx_dma))
1186 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1189 spin_lock_irq(&uap->port.lock);
1190 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1191 pl011_write(uap->dmacr, uap, REG_DMACR);
1192 spin_unlock_irq(&uap->port.lock);
1194 if (uap->using_tx_dma) {
1196 dmaengine_terminate_all(uap->dmatx.chan);
1197 if (uap->dmatx.queued) {
1198 dma_unmap_single(uap->dmatx.chan->device->dev,
1199 uap->dmatx.dma, uap->dmatx.len,
1201 uap->dmatx.queued = false;
1204 kfree(uap->dmatx.buf);
1205 uap->using_tx_dma = false;
1208 if (uap->using_rx_dma) {
1209 dmaengine_terminate_all(uap->dmarx.chan);
1211 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);
1212 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);
1213 if (uap->dmarx.poll_rate)
1214 del_timer_sync(&uap->dmarx.timer);
1215 uap->using_rx_dma = false;
1219 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1221 return uap->using_rx_dma;
1224 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1226 return uap->using_rx_dma && uap->dmarx.running;
1231 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1235 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1239 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1243 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1248 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1252 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1257 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1261 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1265 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1270 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1275 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1283 static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1289 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
1290 struct uart_port *port = &uap->port;
1302 udelay(uap->rs485_tx_drain_interval);
1309 cr = pl011_read(uap, REG_CR);
1319 pl011_write(cr, uap, REG_CR);
1321 uap->rs485_tx_started = false;
1326 struct uart_amba_port *uap =
1329 uap->im &= ~UART011_TXIM;
1330 pl011_write(uap->im, uap, REG_IMSC);
1331 pl011_dma_tx_stop(uap);
1333 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1334 pl011_rs485_tx_stop(uap);
1337 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1340 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1342 if (pl011_tx_chars(uap, false)) {
1343 uap->im |= UART011_TXIM;
1344 pl011_write(uap->im, uap, REG_IMSC);
1348 static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1350 struct uart_port *port = &uap->port;
1354 cr = pl011_read(uap, REG_CR);
1366 pl011_write(cr, uap, REG_CR);
1371 uap->rs485_tx_started = true;
1376 struct uart_amba_port *uap =
1379 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1380 !uap->rs485_tx_started)
1381 pl011_rs485_tx_start(uap);
1383 if (!pl011_dma_tx_start(uap))
1384 pl011_start_tx_pio(uap);
1389 struct uart_amba_port *uap =
1392 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1394 pl011_write(uap->im, uap, REG_IMSC);
1396 pl011_dma_rx_stop(uap);
1410 struct uart_amba_port *uap =
1413 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1414 pl011_write(uap->im, uap, REG_IMSC);
1417 static void pl011_rx_chars(struct uart_amba_port *uap)
1418 __releases(&uap->port.lock)
1419 __acquires(&uap->port.lock)
1421 pl011_fifo_to_tty(uap);
1423 spin_unlock(&uap->port.lock);
1424 tty_flip_buffer_push(&uap->port.state->port);
1429 if (pl011_dma_rx_available(uap)) {
1430 if (pl011_dma_rx_trigger_dma(uap)) {
1431 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1433 uap->im |= UART011_RXIM;
1434 pl011_write(uap->im, uap, REG_IMSC);
1438 if (uap->dmarx.poll_rate) {
1439 uap->dmarx.last_jiffies = jiffies;
1440 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1441 mod_timer(&uap->dmarx.timer,
1443 msecs_to_jiffies(uap->dmarx.poll_rate));
1448 spin_lock(&uap->port.lock);
1451 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1455 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1458 pl011_write(c, uap, REG_DR);
1459 uap->port.icount.tx++;
1465 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1467 struct circ_buf *xmit = &uap->port.state->xmit;
1468 int count = uap->fifosize >> 1;
1470 if (uap->port.x_char) {
1471 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1473 uap->port.x_char = 0;
1476 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1477 pl011_stop_tx(&uap->port);
1482 if (pl011_dma_tx_irq(uap))
1489 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1496 uart_write_wakeup(&uap->port);
1499 pl011_stop_tx(&uap->port);
1505 static void pl011_modem_status(struct uart_amba_port *uap)
1509 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1511 delta = status ^ uap->old_status;
1512 uap->old_status = status;
1518 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1520 if (delta & uap->vendor->fr_dsr)
1521 uap->port.icount.dsr++;
1523 if (delta & uap->vendor->fr_cts)
1524 uart_handle_cts_change(&uap->port,
1525 status & uap->vendor->fr_cts);
1527 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1530 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1532 if (!uap->vendor->cts_event_workaround)
1536 pl011_write(0x00, uap, REG_ICR);
1543 pl011_read(uap, REG_ICR);
1544 pl011_read(uap, REG_ICR);
1549 struct uart_amba_port *uap = dev_id;
1554 spin_lock_irqsave(&uap->port.lock, flags);
1555 status = pl011_read(uap, REG_RIS) & uap->im;
1558 check_apply_cts_event_workaround(uap);
1562 uap, REG_ICR);
1565 if (pl011_dma_rx_running(uap))
1566 pl011_dma_rx_irq(uap);
1568 pl011_rx_chars(uap);
1572 pl011_modem_status(uap);
1574 pl011_tx_chars(uap, true);
1579 status = pl011_read(uap, REG_RIS) & uap->im;
1584 spin_unlock_irqrestore(&uap->port.lock, flags);
1591 struct uart_amba_port *uap =
1595 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1597 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1603 struct uart_amba_port *uap =
1606 unsigned int status = pl011_read(uap, REG_FR);
1613 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1614 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1615 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1622 struct uart_amba_port *uap =
1626 cr = pl011_read(uap, REG_CR);
1646 pl011_write(cr, uap, REG_CR);
1651 struct uart_amba_port *uap =
1656 spin_lock_irqsave(&uap->port.lock, flags);
1657 lcr_h = pl011_read(uap, REG_LCRH_TX);
1662 pl011_write(lcr_h, uap, REG_LCRH_TX);
1663 spin_unlock_irqrestore(&uap->port.lock, flags);
1670 struct uart_amba_port *uap =
1673 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1687 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1693 struct uart_amba_port *uap =
1703 status = pl011_read(uap, REG_FR);
1707 return pl011_read(uap, REG_DR);
1713 struct uart_amba_port *uap =
1716 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1719 pl011_write(ch, uap, REG_DR);
1726 struct uart_amba_port *uap =
1736 retval = clk_prepare_enable(uap->clk);
1740 uap->port.uartclk = clk_get_rate(uap->clk);
1745 uap, REG_ICR);
1751 uap->im = pl011_read(uap, REG_IMSC);
1752 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1754 if (dev_get_platdata(uap->port.dev)) {
1757 plat = dev_get_platdata(uap->port.dev);
1764 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1766 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1767 pl011_reg_to_offset(uap, REG_LCRH_TX);
1770 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1772 pl011_write(lcr_h, uap, REG_LCRH_RX);
1773 if (pl011_split_lcrh(uap)) {
1780 pl011_write(0xff, uap, REG_MIS);
1781 pl011_write(lcr_h, uap, REG_LCRH_TX);
1785 static int pl011_allocate_irq(struct uart_amba_port *uap)
1787 pl011_write(uap->im, uap, REG_IMSC);
1789 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1797 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1802 spin_lock_irqsave(&uap->port.lock, flags);
1805 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1813 for (i = 0; i < uap->fifosize * 2; ++i) {
1814 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1817 pl011_read(uap, REG_DR);
1820 uap->im = UART011_RTIM;
1821 if (!pl011_dma_rx_running(uap))
1822 uap->im |= UART011_RXIM;
1823 pl011_write(uap->im, uap, REG_IMSC);
1824 spin_unlock_irqrestore(&uap->port.lock, flags);
1829 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1832 spin_lock_irqsave(&uap->port.lock, flags);
1834 uap->im = UART011_RTIM;
1835 if (!pl011_dma_rx_running(uap))
1836 uap->im |= UART011_RXIM;
1838 pl011_write(uap->im, uap, REG_IMSC);
1840 spin_unlock_irqrestore(&uap->port.lock, flags);
1845 struct uart_amba_port *uap =
1854 retval = pl011_allocate_irq(uap);
1858 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1860 spin_lock_irq(&uap->port.lock);
1862 cr = pl011_read(uap, REG_CR);
1869 pl011_write(cr, uap, REG_CR);
1871 spin_unlock_irq(&uap->port.lock);
1876 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1879 pl011_dma_startup(uap);
1881 pl011_enable_interrupts(uap);
1886 clk_disable_unprepare(uap->clk);
1892 struct uart_amba_port *uap =
1900 retval = pl011_allocate_irq(uap);
1905 uap->old_status = 0;
1907 pl011_enable_interrupts(uap);
1912 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1917 val = pl011_read(uap, lcrh);
1919 pl011_write(val, uap, lcrh);
1927 static void pl011_disable_uart(struct uart_amba_port *uap)
1931 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1932 spin_lock_irq(&uap->port.lock);
1933 cr = pl011_read(uap, REG_CR);
1936 pl011_write(cr, uap, REG_CR);
1937 spin_unlock_irq(&uap->port.lock);
1942 pl011_shutdown_channel(uap, REG_LCRH_RX);
1943 if (pl011_split_lcrh(uap))
1944 pl011_shutdown_channel(uap, REG_LCRH_TX);
1947 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1949 spin_lock_irq(&uap->port.lock);
1952 uap->im = 0;
1953 pl011_write(uap->im, uap, REG_IMSC);
1954 pl011_write(0xffff, uap, REG_ICR);
1956 spin_unlock_irq(&uap->port.lock);
1961 struct uart_amba_port *uap =
1964 pl011_disable_interrupts(uap);
1966 pl011_dma_shutdown(uap);
1968 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1969 pl011_rs485_tx_stop(uap);
1971 free_irq(uap->port.irq, uap);
1973 pl011_disable_uart(uap);
1978 clk_disable_unprepare(uap->clk);
1982 if (dev_get_platdata(uap->port.dev)) {
1985 plat = dev_get_platdata(uap->port.dev);
1990 if (uap->port.ops->flush_buffer)
1991 uap->port.ops->flush_buffer(port);
1996 struct uart_amba_port *uap =
1999 pl011_disable_interrupts(uap);
2001 free_irq(uap->port.irq, uap);
2003 if (uap->port.ops->flush_buffer)
2004 uap->port.ops->flush_buffer(port);
2043 struct uart_amba_port *uap =
2050 if (uap->vendor->oversampling)
2064 if (uap->dmarx.auto_poll_rate)
2065 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2096 if (uap->fifosize > 1)
2113 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
2123 old_cr = pl011_read(uap, REG_CR);
2136 if (uap->vendor->oversampling) {
2149 if (uap->vendor->oversampling) {
2156 pl011_write(quot & 0x3f, uap, REG_FBRD);
2157 pl011_write(quot >> 6, uap, REG_IBRD);
2165 pl011_write_lcr_h(uap, lcr_h);
2173 pl011_write(old_cr, uap, REG_CR);
2182 struct uart_amba_port *uap =
2186 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2194 uart_update_timeout(port, CS8, uap->fixed_baud);
2201 struct uart_amba_port *uap =
2203 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2235 struct uart_amba_port *uap =
2239 pl011_rs485_tx_stop(uap);
2243 u32 cr = pl011_read(uap, REG_CR);
2246 pl011_write(cr, uap, REG_CR);
2313 struct uart_amba_port *uap =
2316 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2318 pl011_write(ch, uap, REG_DR);
2324 struct uart_amba_port *uap = amba_ports[co->index];
2329 clk_enable(uap->clk);
2332 if (uap->port.sysrq)
2335 locked = spin_trylock(&uap->port.lock);
2337 spin_lock(&uap->port.lock);
2342 if (!uap->vendor->always_enabled) {
2343 old_cr = pl011_read(uap, REG_CR);
2346 pl011_write(new_cr, uap, REG_CR);
2349 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2356 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2357 & uap->vendor->fr_busy)
2359 if (!uap->vendor->always_enabled)
2360 pl011_write(old_cr, uap, REG_CR);
2363 spin_unlock(&uap->port.lock);
2366 clk_disable(uap->clk);
2369 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2372 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2375 lcr_h = pl011_read(uap, REG_LCRH_TX);
2390 ibrd = pl011_read(uap, REG_IBRD);
2391 fbrd = pl011_read(uap, REG_FBRD);
2393 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2395 if (uap->vendor->oversampling) {
2396 if (pl011_read(uap, REG_CR)
2405 struct uart_amba_port *uap;
2419 uap = amba_ports[co->index];
2420 if (!uap)
2424 pinctrl_pm_select_default_state(uap->port.dev);
2426 ret = clk_prepare(uap->clk);
2430 if (dev_get_platdata(uap->port.dev)) {
2433 plat = dev_get_platdata(uap->port.dev);
2438 uap->port.uartclk = clk_get_rate(uap->clk);
2440 if (uap->vendor->fixed_options) {
2441 baud = uap->fixed_baud;
2447 pl011_console_get_options(uap, &baud, &parity, &bits);
2450 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2688 static void pl011_unregister_port(struct uart_amba_port *uap)
2694 if (amba_ports[i] == uap)
2699 pl011_dma_remove(uap);
2715 static int pl011_get_rs485_mode(struct uart_amba_port *uap)
2717 struct uart_port *port = &uap->port;
2727 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2739 uap->port.dev = dev;
2740 uap->port.mapbase = mmiobase->start;
2741 uap->port.membase = base;
2742 uap->port.fifosize = uap->fifosize;
2743 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2744 uap->port.flags = UPF_BOOT_AUTOCONF;
2745 uap->port.line = index;
2747 ret = pl011_get_rs485_mode(uap);
2751 amba_ports[index] = uap;
2756 static int pl011_register_port(struct uart_amba_port *uap)
2761 pl011_write(0, uap, REG_IMSC);
2762 pl011_write(0xffff, uap, REG_ICR);
2767 dev_err(uap->port.dev,
2770 if (amba_ports[i] == uap)
2776 ret = uart_add_one_port(&amba_reg, &uap->port);
2778 pl011_unregister_port(uap);
2792 struct uart_amba_port *uap;
2801 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2803 if (!uap)
2806 uap->clk = devm_clk_get(&dev->dev, NULL);
2807 if (IS_ERR(uap->clk))
2808 return PTR_ERR(uap->clk);
2810 uap->reg_offset = vendor->reg_offset;
2811 uap->vendor = vendor;
2812 uap->fifosize = vendor->get_fifosize(dev);
2813 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2814 uap->port.irq = dev->irq[0];
2815 uap->port.ops = &amba_pl011_pops;
2816 uap->port.rs485_config = pl011_rs485_config;
2817 uap->port.rs485_supported = pl011_rs485_supported;
2818 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2823 uap->port.iotype = UPIO_MEM;
2826 uap->port.iotype = UPIO_MEM32;
2835 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2839 amba_set_drvdata(dev, uap);
2841 return pl011_register_port(uap);
2846 struct uart_amba_port *uap = amba_get_drvdata(dev);
2848 uart_remove_one_port(&amba_reg, &uap->port);
2849 pl011_unregister_port(uap);
2855 struct uart_amba_port *uap = dev_get_drvdata(dev);
2857 if (!uap)
2860 return uart_suspend_port(&amba_reg, &uap->port);
2865 struct uart_amba_port *uap = dev_get_drvdata(dev);
2867 if (!uap)
2870 return uart_resume_port(&amba_reg, &uap->port);
2878 struct uart_amba_port *uap;
2901 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2903 if (!uap)
2909 uap->port.irq = ret;
2914 uap->vendor = &vendor_qdt_qdf2400_e44;
2917 uap->vendor = &vendor_sbsa;
2919 uap->reg_offset = uap->vendor->reg_offset;
2920 uap->fifosize = 32;
2921 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2922 uap->port.ops = &sbsa_uart_pops;
2923 uap->fixed_baud = baudrate;
2925 snprintf(uap->type, sizeof(uap->type), "SBSA");
2929 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2933 platform_set_drvdata(pdev, uap);
2935 return pl011_register_port(uap);
2940 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2942 uart_remove_one_port(&amba_reg, &uap->port);
2943 pl011_unregister_port(uap);