Lines Matching defs:pl011_read
285 static unsigned int pl011_read(const struct uart_amba_port *uap,
318 status = pl011_read(uap, REG_FR);
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
774 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
1186 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1309 cr = pl011_read(uap, REG_CR);
1354 cr = pl011_read(uap, REG_CR);
1455 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1509 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1543 pl011_read(uap, REG_ICR);
1544 pl011_read(uap, REG_ICR);
1555 status = pl011_read(uap, REG_RIS) & uap->im;
1579 status = pl011_read(uap, REG_RIS) & uap->im;
1595 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1606 unsigned int status = pl011_read(uap, REG_FR);
1626 cr = pl011_read(uap, REG_CR);
1657 lcr_h = pl011_read(uap, REG_LCRH_TX);
1673 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1687 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1703 status = pl011_read(uap, REG_FR);
1707 return pl011_read(uap, REG_DR);
1716 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1751 uap->im = pl011_read(uap, REG_IMSC);
1814 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1817 pl011_read(uap, REG_DR);
1862 cr = pl011_read(uap, REG_CR);
1876 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1917 val = pl011_read(uap, lcrh);
1933 cr = pl011_read(uap, REG_CR);
2123 old_cr = pl011_read(uap, REG_CR);
2243 u32 cr = pl011_read(uap, REG_CR);
2316 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2343 old_cr = pl011_read(uap, REG_CR);
2356 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2372 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2375 lcr_h = pl011_read(uap, REG_LCRH_TX);
2390 ibrd = pl011_read(uap, REG_IBRD);
2391 fbrd = pl011_read(uap, REG_FBRD);
2396 if (pl011_read(uap, REG_CR)