Lines Matching refs:membase
65 cr = readb(uap->port.membase + UART010_CR);
67 writel(cr, uap->port.membase + UART010_CR);
76 cr = readb(uap->port.membase + UART010_CR);
78 writel(cr, uap->port.membase + UART010_CR);
87 cr = readb(uap->port.membase + UART010_CR);
89 writel(cr, uap->port.membase + UART010_CR);
97 cr = readb(uap->port.membase + UART010_CR);
99 writel(cr, uap->port.membase + UART010_CR);
108 cr = readb(uap->port.membase + UART010_CR);
110 writel(cr, uap->port.membase + UART010_CR);
118 status = readb(port->membase + UART01x_FR);
120 ch = readb(port->membase + UART01x_DR);
129 rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
131 writel(0, port->membase + UART01x_ECR);
161 status = readb(port->membase + UART01x_FR);
172 writel(ch, port->membase + UART01x_DR),
181 writel(0, port->membase + UART010_ICR);
183 status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
212 status = readb(port->membase + UART010_IIR);
225 status = readb(port->membase + UART010_IIR);
238 unsigned int status = readb(port->membase + UART01x_FR);
248 status = readb(port->membase + UART01x_FR);
265 uap->data->set_mctrl(uap->dev, port->membase, mctrl);
274 lcr_h = readb(port->membase + UART010_LCRH);
279 writel(lcr_h, port->membase + UART010_LCRH);
308 uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
314 port->membase + UART010_CR);
337 writel(0, port->membase + UART010_CR);
340 writel(readb(port->membase + UART010_LCRH) &
342 port->membase + UART010_LCRH);
423 old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
430 writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
431 writel(quot & 0xff, port->membase + UART010_LCRL);
438 writel(lcr_h, port->membase + UART010_LCRH);
439 writel(old_cr, port->membase + UART010_CR);
538 status = readb(port->membase + UART01x_FR);
541 writel(ch, port->membase + UART01x_DR);
556 old_cr = readb(port->membase + UART010_CR);
557 writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
566 status = readb(port->membase + UART01x_FR);
569 writel(old_cr, port->membase + UART010_CR);
578 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
580 lcr_h = readb(uap->port.membase + UART010_LCRH);
595 quot = readb(uap->port.membase + UART010_LCRL) |
596 readb(uap->port.membase + UART010_LCRM) << 8;
691 uap->port.membase = base;